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riscv-non-isa / riscv-ap-tee

This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.
https://jira.riscv.org/browse/RVG-76
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[Qualcomm feedback] Chapter 4: Section 4.2 Clarify TSM must be in confidential memory #49

Closed rsahita closed 6 months ago

rsahita commented 7 months ago

Reference: link

T1: Loss of confidentiality of TVMs and TSM memory via in-scope adversaries that may read TSM/TVM memory via CPU accesses

replace memory with private memory? There is no definition of "private" memory, I don't believe TSM can use any memory which is not "private". Only TVMs can have both shared and confidential memory.

rsahita commented 6 months ago

changed this to say:

T1: Loss of confidentiality of TVMs and TSM confidential memory via in-scope adversaries that may read TSM/TVM confidential memory via CPU

rsahita commented 6 months ago

address in PR #71

cc @ozkoyuncu

ozkoyuncu commented 6 months ago

Agreed, could not find reference to private memory in the doc either. the comment is a bit confusing as what it is suggesting. I think it is ok