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riscv-non-isa / riscv-ap-tee

This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.
https://jira.riscv.org/browse/RVG-76
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[Qualcomm feedback] Chapter 5.1: Clarification on MTT programming #55

Closed rsahita closed 7 months ago

rsahita commented 9 months ago

Reference: link

Confidential and non-confidential memory are both always assigned by the VMM - the TSM and TSM-driver are expected to manage the isolation for confidential memory by programming the Memory Tracking Table (MTT).

Why does the TSM need to be involved in the programming of the MTT? why is it not only concerned with finer grained isolation facilitated by the G-stage page table?

Also considering the case of multiple TEEs / TSMs. I think the point here is that TSM is administratively involved, but the enforcement of memory isolation between SDs can only be done by M-mode TSM driver. Some rephrasing is requested to make this more clear.

rsahita commented 7 months ago

fixed - the TSM-driver is expected to manage isolation.

rsahita commented 7 months ago

Closing as addressed in PR #70 cc @ozkoyuncu