This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.
The host can handle exits caused by virtual instruction by examining and decoding the contents of the NACL shared memory region.
Presumably the TSM would first to handle the virtual instruction exception, but I can't imagine it passing it on to the host. In particular the host does not / should not have access to guest confidential memory. Are there examples of how this might be used?
Presumably the TSM would first to handle the virtual instruction exception, but I can't imagine it passing it on to the host. In particular the host does not / should not have access to guest confidential memory. Are there examples of how this might be used?