search

riscv-non-isa / riscv-arch-test

https://jira.riscv.org/browse/RVG-141?src=confmacro
Apache License 2.0
514 stars 199 forks source link

Missing RV32i/RV64i test: FenceI #119

Open allenjbaum opened 4 years ago

allenjbaum commented 4 years ago

(attribution: AWaterman, edited ) FENCE is in the base ISA, but there is no test in the Base ISA test suite for it.

For compliance testing purposes on a uniprocessor, all you can do is check that it executes as a NOP. All bits besides opcode/funct3 are supposed to be ignored. You should make sure that setting all the other 22 bits doesn’t raise an exception. (You’ll need to use an assembler hack to do so, since there’s currently no assembler syntax that can set all the bits in a FENCE instruction, so you'll need to encode it as a hex constant))

Theoretically, RVWMO vs. RVTSO should be able to perform a real test, but not on a uniprocessor obviously.

The RVWMO litmus tests should eventually be part of some compliance suite, but since they’re multithreaded programs but not for this base ISA compliance suite.

allenjbaum commented 4 years ago

Title has been corrected, test is included in the updated base ISA tests. This will be closed when those tests are merged

allenjbaum commented 3 years ago

The title was originally Fence, but I changed it to FenceI, despite the fact that Andrew's comment was specifically about Fence. The comments, in fact, pretty much apply to both. Fence is guaranteed to be a hint; Fence.I is not, but in both cases, setting any of the reserved bits to one should not cause a trap. Neither the Fence nor Fence.I tests check for that.

allenjbaum commented 2 years ago

Need to write fence test that use tool-chain unsupported encodings and verify that they trap (also need to change any la/li to be LA/LI)...

allenjbaum commented 1 year ago

Add this as a separate test, not part of existing test