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riscv-non-isa / riscv-arch-test

https://jira.riscv.org/browse/RVG-141?src=confmacro
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Privilege mode test #170

Closed panda1628 closed 3 years ago

panda1628 commented 3 years ago

I am looking for privilege mode tests (e.g. machine, supervisor and user) Switching between different modes and access different privilege CSRs cause exceptions

Are they WIP?

allenjbaum commented 3 years ago

The work on those is just being started. Three are some older tests, with minimal coverage in the riscv-tests directory, but the are pretty basic and are incompatible with the current framework.

On Fri, Feb 19, 2021 at 1:05 AM panda1628 notifications@github.com wrote:

I am looking for privilege mode tests (e.g. machine, supervisor and user) Switching between different modes and access different privilege CSRs cause exceptions

Are they WIP?

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panda1628 commented 3 years ago

Thank you for the update. Let me know if I can help

allenjbaum commented 3 years ago

Bit of a late reply - I've been trying to figure out how you can help. Without knowing your background, it is hard to say. First: you probably should join the sig-arch-test mailing list here: https://lists.riscv.org/g/sig-arch-test/

The next major project is to transition to framework 3.0. That framework will

The biggest prerequisite to getting this done is currently retrofitting the Sail model to e able to configure itself. We are hoping that RIOS Labs - a group contributor" may take on that work.

The next prerequisite is a test-plan for the privileged architecture: what are we going to generate tests for, what are the cover points that we need to hit to show that we've tested enough. That results in a YAML format file that is used to measure the quality of the tests, and discover if we've missed any corner cases.

Finally, we have to generate tests. This should be done by writing test generators - probably for each priv feature on a section by section basis. In theory, that will be done by another group contributor. (also RIOS Labs?)

We are starting up a Simulator SIG, and are looking for a chair to drive it. The role of that SIG is to manage / guide the development of our simulator technology by these group contributors. That includes Sail, Spike and QEMU - and possibly GEM for some cases. We have a vice-chair nominatoed.

Beyond that, there is the management of whoever is writing tests: reviewing tests plans and managing/guiding development of tests.

On the arch-test-sig side, we need to maintain the existing framework, and also evolve it to handle non-deterministic results, memory mode/coherency, and asynchronous events. Some of that will require an entirely different approach than what we are doing now, so that will need to be architected

I'm also nominally in charge of

With all the work list above: do you see anything that you'd like to help out with?

On Sat, Feb 20, 2021 at 12:28 AM panda1628 notifications@github.com wrote:

Thank you for the update. Let me know if I can help

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allenjbaum commented 3 years ago

question answered, closing this issue