Closed Timmmm closed 1 month ago
Is this available in GCC and LLVM?
It is.
@Timmmm perhaps worth giving an example using the named opcode as well (e.g. .insn r MADD, 0, 0, fa0, fa1, fa2, fa3
).
I added .insn r OP, 0, 0, a0, a1, a2
so it's the same instruction as the other examples.
Closing this as https://github.com/riscv-non-isa/riscv-asm-manual/pull/109 was merged.
Add .insn directive with brief description and link to full documentation.