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riscv-non-isa / riscv-asm-manual

RISC-V Assembly Programmer's Manual
https://jira.riscv.org/browse/RVG-4
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Typos #62

Closed montedalrymple closed 3 years ago

montedalrymple commented 3 years ago

In the section "A listing of standard RISC-V pseudoinstructions" the descriptions for call and tail specify x6. Should be x1?

aswaterman commented 3 years ago

No, this is intentional. We don’t want to push anything to a return-address stack in the case of a tail call, so we want to use a register other than x1 or x5. x6 is a convenient choice because in the standard ABIs it’s a temporary register.

montedalrymple commented 3 years ago

Okay, then table 25.3 in the ISA manual needs to be changed. It says CALL uses x1.

montedalrymple commented 3 years ago

Never mind. Just realized that chapter in the ISA manual is going away.

aswaterman commented 3 years ago

I did check the assembly manual, and it looks correct. CALL uses x1 and TAIL uses x6 and that's by design.