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riscv-non-isa / riscv-brs

The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.
https://jira.riscv.org/browse/RVG-48
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Many JEP106 manufacturer codes do not fit in 4 bytes #168

Closed jhauser-us closed 3 months ago

jhauser-us commented 3 months ago

In Section 7.1, "Type 04 Processor Information", we have:

The first DWORD (offsets 08h-0Bh) is the JEP-106 code for the vendor.

JEP106 defines a manufacturer’s identification code as a variable number of bytes, consisting of zero or more 0x7F bytes followed by a final byte that is not 0x7F. For all recently registered manufacturers, this sequence is longer than four bytes. For example, I believe the code for SiFive is a sequence of 10 bytes: (in hexadecimal) 7F 7F 7F 7F 7F 7F 7F 7F 7F 89. The document does not currently explain how this is going to be made to fit in the first four bytes of the Processor ID field of a Processor Information structure.

Please note that there is no one standard encoding for compressing the string of 0x7F prefixes, so if such an encoding is intended, it should not be assumed to be obvious common knowledge.

ved-rivos commented 3 months ago

The Priv. Spec mvendorid register implements a compression scheme where bits 6:0 is the ID without the parity and the bits 31:7 represent the number of continuation codes (e.g., 0x509). This specification could just state that DWORD holds the value in mvendorid of hart 0 (The section 7.5.3.4 of DSP0134 that is superseded by this specification specified the Processor ID QWORD as holding mvendorid of hart 0).

andreiw commented 3 months ago

I'll write it out, because the value may be a soc ID - not a vendor id (the soc vendor may differ from hart vendor).