Add inline asm operand constraints for vector register

riscv-non-isa / riscv-c-api-doc

Documentation of the RISC-V C API

https://jira.riscv.org/browse/RVG-4

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Closed kito-cheng closed 1 year ago

kito-cheng commented 1 year ago

We have 3 common operand constraints constraint between GCC and LLVM here:

vr: Any vector register, v0-v31
vd: Any vector register, excluding v0, used for avoid overlapping with mask register.
vm: Mask vector register, only v0.

cmuellner commented 1 year ago

The description of this PR mixes 'vd' and 'vm'. However, the actual change in the commit is correct and corresponds to the GCC implementation. LGTM.

kito-cheng commented 1 year ago

Fixed commit log :P