riscv-non-isa / riscv-c-api-doc

Documentation of the RISC-V C API
https://jira.riscv.org/browse/RVG-4
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Using vector intrinsics with `__attribute__((target("arch=+v")))` #69

Open camel-cdr opened 6 months ago

camel-cdr commented 6 months ago

It is currently not possible (on gcc and clang) to use the vector intrinsics in functions with a target attribute that adds vector support, if it vector support wasn't also enabled globally.

This is needed for implementing dynamic dispatch in the same translation unit, as e.g. used in simdutf.

The current compiler implementations aren't wrong to only allow including <riscv_vector.h> and defining __riscv_v_intrinsic, when the vector extension is enabled globally, but I think we should encourage implementations to view __riscv_v_intrinsic and __riscv_vector separately, when possible.

Something along the lines of "__riscv_v_intrinsic being defined doesn't guarantee that __riscv_vector is also defined."

From what I can tell this isn't required by the spec anywhere, but implementers assumed the opposite is implied.

The __riscv_v_intrinsic macro is the C macro to test the compiler’s support for the RISC-V "V" extension intrinsics

__riscv_vector [...] Implies that any of the vector extensions (v or zve*) is available

This would suggest, that __riscv_v_intrinsic does not automatically imply __riscv_vector is defined.

topperc commented 6 months ago

For clang this needs a lot of work. For example, the code in SemaChecking.cpp that checks for valid rvv vector types is completely unaware of the existence of attribute((target)).

camel-cdr commented 6 months ago

Alright, good to know, I was wondering if it might just be harder to implement. It's not a really high priority thing.

kito-cheng commented 6 months ago

We (SiFive) have assigned engineer resource on clang side, and will try to find people to enable that on gcc side :)

4vtomat commented 6 months ago

I have a PR for this: https://github.com/llvm/llvm-project/pull/83674.