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riscv-non-isa / riscv-external-debug-security

The RISC-V External Debug Security Specification
https://jira.riscv.org/browse/RVG-136
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Mandate the behavior of asynchronous trigger #14

Closed joxie closed 7 months ago

joxie commented 7 months ago

https://github.com/joxie/riscv-debug-security/issues/16

AoteJin commented 7 months ago

The description in external debug security spec addressed the issue:

"The extension requires that all pending triggers intending to enter Debug Mode must match or fire before any hart mode switch to prevent privilege escalation."