riscv-non-isa / riscv-external-debug-security

The RISC-V External Debug Security Specification
https://jira.riscv.org/browse/RVG-136
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aamvirtual restriction is not required #35

Closed gokhankaplayan closed 3 months ago

gokhankaplayan commented 4 months ago

The following restriction about aamvirtual does not make sense to me for two reasons:

The field aamvirtual in command (at 0x17) determines whether physical or virtual address translation is employed. However, when mdbgen[i] is 0, the extension mandates that aamvirtual is hardwire to 1 and memory access addresses are processed as if initiated by the hart in debug access privilege.

As a result, I proposed to remove this restriction from the spec.

AoteJin commented 3 months ago

We need to consider the corner case when mstatus.TVM is 0x1. In this case, the virtual translation cannot be disabled in S-mode. If we remove aamvirtual restriction, there will be a hole when mstatus.TVM is 0x1.

gokhankaplayan commented 3 months ago

Thank you for the explanation @AoteJin. I was not aware of TVM bit setting. I am closing the ticket.