Add stselect to regs whose access is controlled by xstateen0.TR

riscv-non-isa / riscv-external-debug-security

The RISC-V External Debug Security Specification

https://jira.riscv.org/browse/RVG-136

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Closed bcstrongx closed 2 months ago

bcstrongx commented 2 months ago

Fix an oversight.

bcstrongx commented 2 months ago

@joxie @gokhankaplayan @AoteJin FYI, I realized I missed stselect in the state enable section, so I fixed it and went ahead with the merge.