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riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
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bug fix - issue 240 #241

Closed ved-rivos closed 1 year ago

ved-rivos commented 1 year ago

hpm counters were modeled as 63 bits - should be 64-bit