riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
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How should the host bridge handle it abort the no corresponding field when use tr_req_ctl ? #248

Closed baimengwei closed 1 year ago

baimengwei commented 1 year ago

The tr_req_ctl register and the request initiated by the host bridge to IOMMU do not fully correspond. How should the host bridge handle it abort the no corresponding field when use tr_req_ctl ?

the tr_req_ctl register is at here:

  {bits: 1, name: 'Go/Busy'},
  {bits: 1, name: 'Priv'},
  {bits: 1, name: 'Exe'},
  {bits: 1, name: 'NW'},
  {bits: 8, name: 'reserved'},
  {bits: 20, name: 'PID'},
  {bits: 1, name: 'PV'},
  {bits: 3, name: 'reserved'},
  {bits: 4, name: 'custom'},
  {bits: 24, name: 'DID'},

the request initiated by the host bridge to IOMMU is at here:

typedef struct {
    addr_type_t at;
    uint64_t    iova;
    uint32_t    length;
    uint8_t     read_writeAMO;
} iommu_trans_req_t;

// Request to IOMMU from the host bridge
typedef struct {
    // Device ID input
    uint32_t device_id;
    // Process ID input (e.g. PASID present)
    uint8_t  pid_valid;
    uint32_t process_id;
    uint8_t  no_write;
    uint8_t  exec_req;
    uint8_t  priv_req;
    uint8_t  is_cxl_dev;
    // Translation request
    iommu_trans_req_t tr;
} hb_to_iommu_req_t;

the part of no corresponding is here:

addr_type_t 
is_cxl_dev
length
read_writeAMO

If using tr_req_ctl register for sending a request, but the information received by the host bridge seems insufficient. Some control signals used in the request seems not undefined. Am I right in understanding this way?

ved-rivos commented 1 year ago

debug interface is not invoked by the host bridge.