Can you clarify "command-queue access"

[hsxyb]

Can you clarify what does "command-queue access" mean in description of cqmf ? Does it include command queue read access and the write access of IOFENCE.C command with AV=1? https://github.com/riscv-non-isa/riscv-iommu/blob/61026efa47a8a4fdcf301788044aba2308add3bf/iommu_registers.adoc?plain=1#L782-L786

[ved-rivos]

Does it include command queue read access and the write access of IOFENCE.C command with AV=1?

Yes. It includes both.

[ved-rivos]

Would be a good clarification to include - see https://github.com/riscv-non-isa/riscv-iommu/pull/243/commits/69026209b298751ad6b3ee1e7ee928262d82b222.

[wangyongzhen0322]

If the write access failure of IOFENCE.C command with AV=1 will set the cqmf to 1, the cqh will reference the IOFENCE.C command. But a IOFENCE.C command completion is determined by cqh advancing past the index of the IOFENCE.C command in the CQ and the IOMMU writes data to memory with AV=1 when the IOFENCE.C command completes. It seems that there is confusion in the description of the spec. When a write access leads a failure with AV=1, wheather the IOFENCE.C is complete?Using only cqh and cqmf does not seem to be enough; it cannot indicate both IOFENCE.C completion and memory failure.

[ved-rivos]

When a write access leads a failure with AV=1, wheather the IOFENCE.C is complete?

The IOFENCE.C is not complete because it encounters a memory fault.

[wangyongzhen0322]

Thanks for your answer. And could you consider revising the sentence in the spec, as it reads very ambiguously in terms of time relationships?

If AV=1, the IOMMU writes DATA to memory at a 4-byte aligned address ADDR[63:2] * 4 as a 4-byte store when the command completes.

[wangyongzhen0322]

And in the function do_fence_c, the bit fence_w_ip will be set to 1 no matter whether the write access is successful if the AV=1. So is there an error in the c_model?

[ved-rivos]

And in the function do_fence_c, the bit fence_w_ip will be set to 1 no matter whether the write access is successful if the AV=1. So is there an error in the c_model?

Yes, the fence_w_ip interrupt signaling should happen after the memory write. Updated in #367

[ved-rivos]

And could you consider revising the sentence in the spec, as it reads very ambiguously in terms of time relationships?

The DATA is written to the ADDR if the command completes but if the write to ADDR faults then no data is written i.e. no data is written unless the command completes and completing the command involves writing the data. Included a clarification here https://github.com/riscv-non-isa/riscv-iommu/pull/243/commits/a3b06a2808856ce1a7321ef64d54d969c1498db1