riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
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Question about VA fault detection in system both support Sv32 and Sv39 #285

Closed viktoryou closed 4 months ago

viktoryou commented 4 months ago

In such IOMMU implementation with capabilities.Sv32=1 & capabilities.Sv39=1 and 64-bit addresss width, as the IOMMU model suggests, when iosatp.MODE=Sv32 and DC.SXL=1, 63–32 should all equal to bit 31, or else a page-fault exception will occur.

While I think this is not exactly what the IOMMU spec requires:

When SXL is 1, the following rules apply:

  • If the first-stage is not Bare, then a page fault corresponding to the original access type occurs if the IOVA has bits beyond bit 31 set to 1.
  • If the second-stage is not Bare, then a guest page fault corresponding to the original access type occurs if the incoming GPA has bits beyond bit 33 set to 1.

I prefer this is a bug in the model (see code), since in a 32-bit system, there is no such canonical rule for Sv32 as Sv39/Sv48/Sv57 in 64-bit system. The check may only detect the [63:32] for IOVA and [63:34] for GPA not to one.

ved-rivos commented 4 months ago

You are right that the code would produce a wrong result for 0xFFFFFFFF_???????? case for SXL=1. Fixing as follows in PR #286 :

if ( (masked_upper_bits != 0 && masked_upper_bits != mask && SXL == 0) ||
     (masked_upper_bits != 0 && SXL == 1) ) goto page_fault;