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riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
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Question about fence_w_ip description with the system configuration #296

Closed viktoryou closed 3 months ago

viktoryou commented 3 months ago

In the chapter 5.15 of the Spec,

An IOMMU that supports only wire-signaled-interrupts sets the fence_w_ip bit to indicate completion of an IOFENCE.C command. To re-enable interrupts on IOFENCE.C completion, software should clear this bit by writing 1. This bit is reserved if the IOMMU does not support wire-signaled-interrupts or wire-signaled-interrupts are not enabled (i.e., fctl.WSI == 0).

This sounds ambiguous. In a system with capabilities.igs=2 (both WSI and MSI interrupt generation mode is supported), would fence_w_ip in cqcsr still be effective when fctl.WSI = 1 and WSI in iofence.c set 1? The bold word only implies that only under capabilities.igs=1 would fence_w_ip bit possibly takes effect, and I guess this is not what we expected.

Please help to clarify this point.

ved-rivos commented 3 months ago

The "only" is extraneous and should be removed (see https://github.com/riscv-non-isa/riscv-iommu/pull/243/commits/3a0bd8dee6a0b882cf2fb38ea5775e3248a01f1a)