Closed baimengwei closed 2 months ago
https://github.com/riscv-non-isa/riscv-iommu/blob/main/iommu_ref_model/libiommu/src/iommu_two_stage_trans.c#L147
if ( (pte->V == 0) || (pte->R == 0 && pte->W == 1) || ((pte->PBMT != 0) && (g_reg_file.capabilities.Svpbmt == 0)) || (pte->PBMT == 3) || (pte->reserved != 0) ) goto page_fault;
if reserved position include RSW bit , it sames that RSW should be zero ?
RSW
if any bits or encodings that are reserved for future standard use are set within pte
https://github.com/riscv-non-isa/riscv-iommu/blob/main/iommu_ref_model/libiommu/include/iommu_translate.h#L31
typedef union { struct { uint64_t V:1; uint64_t R:1; uint64_t W:1; uint64_t X:1; uint64_t U:1; uint64_t G:1; uint64_t A:1; uint64_t D:1; uint64_t RSW:2; uint64_t PPN:44; uint64_t reserved:7; uint64_t PBMT:2; uint64_t N:1; }; uint64_t raw; } pte_t;
RSW bits are reserved for software use and ignored by hardware.
https://github.com/riscv-non-isa/riscv-iommu/blob/main/iommu_ref_model/libiommu/src/iommu_two_stage_trans.c#L147
if reserved position include
RSW
bit , it sames thatRSW
should be zero ?https://github.com/riscv-non-isa/riscv-iommu/blob/main/iommu_ref_model/libiommu/include/iommu_translate.h#L31