Closed zetalog closed 1 month ago
By ATS=1
do you mean the transaction is a memory read with address type set to PCIe ATS Translation Request? For a ATS Translation Request, this case should lead to a response with status value as Success and with Read and Write bits clear. In the code you quote the execution then continues at the label stop_and_report_fault
where the response and whether fault is logged is determined.
2.2.3. Process-context fields
When ENS is 1, supervisor privilege transactions that read with execute intent to pages mapped with U bit in PTE set to 1 are disallowed, regardless of the value of SUM.
According to the above IOMMU specification statements, PnU=1, U=1 should resullt in a translation fault in the reference model regardless of ENS:
This check is enforced regardless of ATS. Then the problem can be seen against the InD=1, ATS=1 sanity check affected by the above code. Following the faulting code path, the reference model could generate faults indicating "instruction S/G stage page fault"; while in DTI-ATS responses, we can only have write, read fault like the following since there is no "executable sence" applicable to the PCIe requesting devices.
This looks reasonable from PCIe's point of view. Shall we change the reference model a bit to be compatible with the real world?