Since the process specified in Section "Two-Stage Address Translation" of the RISC-V Privileged specification is applied in IOMMU, I found that in the model, the dirty bit check is missing when PTE is non-leaf, as well as the access and user bit. Here is what the ratified version of RISC-V Privileged specification said:
For non-leaf PTEs, the D, A, and U bits are reserved for future standard use. Until their use is defined by a standard extension, they must be cleared by software for forward compatibility. (chapter 4.3.2)
if any bits or encodings that are reserved for future standard use are set within pte, stop and raise a page-fault exception corresponding to the original access type. (chapter 4.3.1)
ved-rivos
commented
6 days ago
Since the process specified in Section "Two-Stage Address Translation" of the RISC-V Privileged specification is applied in IOMMU, I found that in the model, the dirty bit check is missing when PTE is non-leaf, as well as the access and user bit. Here is what the ratified version of RISC-V Privileged specification said:
Please help to check.