Question about 4-byte access to IOMMU register ensuring single-copy atomic

riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification

https://jira.riscv.org/browse/RVG-55

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Question about 4-byte access to IOMMU register ensuring single-copy atomic #373

Closed viktoryou closed 6 days ago

viktoryou commented 6 days ago

From the spec,

A 4 byte access to an IOMMU register must be single-copy atomic. Whether an 8 byte access to an IOMMU register is single-copy atomic is UNSPECIFIED.

In the context of using AXI protocol, does it mean that the write strobes must be explicitly checked to ensure at least 4 byte valid access? Since any number of write strobes can be HIGH, the writing data of the register may be less than 4 byte in effect.

ved-rivos commented 6 days ago

Whether an IOMMU supports 1 byte and 2 byte accesses is unspecified. Implementation is not required to support them and software cannot rely on them being supported. For a 4 byte access the implementation must ensure that it is atomic i.e. any side effects of the register write like making register busy must happen only after all 4 bytes of the access have been observed by the register.