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riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
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Should a set of OF in iohpmctr1-31 CSR generate a pmip #380

Closed viktoryou closed 4 months ago

viktoryou commented 4 months ago

From the spec,

The OF bit is set when the iohpmcycles counter overflows, and remains set until cleared by software.

From my understanding, it is also allowed to set the OF by software since the bit has the attribute of RW instead of RW1S. Would the behavior that setting the OF by software be regarded as another counter overflows?

If the iohpmcycles counter overflows when the OF bit is zero, then a HPM Counter Overflow interrupt is generated by setting ipsr.pmip bit to 1. If the OF bit is already one, then no interrupt request is generated. Consequently the OF bit also functions as a count overflow interrupt disable for the iohpmcycles.

Then, should a HPM Counter Overflow interrupt be generated due to setting the OF by software from zero?

ved-rivos commented 4 months ago

It is only the "counter overflows when OF bit is zero" that can cause the interrupt. It is not a 0->1 edge of the OF that sets the interrupt pending. It is the carry out from the counter when OF is 0 that sets the interrupt pending.