search

riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
Creative Commons Attribution 4.0 International
84 stars 16 forks source link

The differences in the behavior of the lower 12 bits of iotval2 between the model and the specification. #394

Closed Taurins-peng closed 4 weeks ago

Taurins-peng commented 1 month ago

When gxl is 0, sxl is 1, iova is 'hfff_ffff_ffff, iosatp is Bare, and iohgatp is SV39X4, a gpgfault occurs, and the model directly changes the lower 2 bits to 0. image Expected scenario: According to the specification, iotval2[11:2] can be 0, however, iotval2[1:0] is determined as described below. image image

ved-rivos commented 1 month ago

Thats right that an IOMMU implementation has the flexibility of a) report the page offset OR b) report 0 for the page offset. An implementation would pick a) or b). The reference implementation does a).

The bit 0 and 1 indicate if the guest page fault was caused due to an implicit access to translate VS stage page tables. When iosatp is Bare, there are no such implicit accesses i.e. there is no VS-stage page table. In such cases the GPA is just the VA.

For guest page faults that occur as a result of VS-stage address translation please see here.

ved-rivos commented 4 weeks ago

Please ask if there are further questions.