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riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
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What type of MSI write access fualt is included in an IOMMU MSI access fault (cause=273)? #404

Closed zhuotianshu closed 1 month ago

zhuotianshu commented 1 month ago

If a normal MSI from a io-device's memory access request cause an access fualt, will IOMMU report a IOMMU MSI access fault? If a notice MSI cause an access fualt, will IOMMU report a IOMMU MSI access fault?

ved-rivos commented 1 month ago

If a normal MSI from a io-device's memory access request cause an access fualt, will IOMMU report a IOMMU MSI access fault?

The IOMMU does not see memory requests. It only sees address translation requests. If the memory access for an MSI leads to an access fault then such transactions are aborted by the IO bridge. When a transaction is aborted the response provided to the device depends on the IO protocol. For PCIe write transactions are posted and so there is no response - the write is discarded. For other protocols like AXI a SLVERR may be generated.

If a notice MSI cause an access fualt, will IOMMU report a IOMMU MSI access fault?

The partitioning of responsibility between IOMMU and IO bridge for recording MSI in an MRIF and generating the notice MSI are implementation specific. An implementation may report a IOMMU MSI access fault if the notice MSI is generated by the IOMMU.

zhuotianshu commented 1 month ago

That's clear, thanks for replying.