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riscv-non-isa / riscv-iommu

RISC-V IOMMU Specification
https://jira.riscv.org/browse/RVG-55
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quetions about iofence.c behavior #430

Closed leBsky closed 2 months ago

leBsky commented 2 months ago

  1. For command iofence.c, if bit[10] av is 1 and ATS command timeouts before this iofence.c command, then no write to memory should occur. Is it correct?

  2. For command iofence.c, if bit[10] av is 1 and iofence completes without any timeout happens, then the command writes the memory. However, if the write is denied by IOPMP or other error occurs, should the cqh still advance by 1 in this case?

ved-rivos commented 2 months ago

For command iofence.c, if bit[10] av is 1 and ATS command timeouts before this iofence.c command, then no write to memory should occur. Is it correct?

When the command times out, it does not complete. The write to memory occurs only if the command completes.

For command iofence.c, if bit[10] av is 1 and iofence completes without any timeout happens, then the command writes the memory. However, if the write is denied by IOPMP or other error occurs, should the cqh still advance by 1 in this case?

If a memory access made by the command itself leads to a memory fault then the command does not complete and instead the command queue stalls with cqcsr.cqmf set to 1. When cqmf is 1, the cqh references the command in the CQ that caused the error.

leBsky commented 2 months ago

For command iofence.c, if bit[10] av is 1 and ATS command timeouts before this iofence.c command, then no write to memory should occur. Is it correct?

When the command times out, it does not complete. The write to memory occurs only if the command completes.

For command iofence.c, if bit[10] av is 1 and iofence completes without any timeout happens, then the command writes the memory. However, if the write is denied by IOPMP or other error occurs, should the cqh still advance by 1 in this case?

If a memory access made by the command itself leads to a memory fault then the command does not complete and instead the command queue stalls with cqcsr.cqmf set to 1. When cqmf is 1, the cqh references the command in the CQ that caused the error.

Clearly. Thanks

yanhe234 commented 1 month ago

Hello sir, currently I am looking at the smmu code for ARM, and it seems that the command timeout is reported through the PCIe side. smmu itself does not have this timeout report. If there is an error, please correct me. How to implement this according to your understanding by setting the cmdto register under RV? How is timeout determined?

ved-rivos commented 1 month ago

The timeout value is specified by the PCIe specifications. Could you clarify more what you mean by "reported through PCIe side"

yanhe234 commented 1 month ago

My understanding is that when RC considers the ATC failure of EP to be incomplete, it will report an interrupt, but smmu did not report the interrupt

ved-rivos commented 1 month ago

Please lookup CERROR_ATC_INV_SYNC and CMD_SYNC.

yanhe234 commented 1 month ago

Hello sir, let me rephrase it as ATS INVAL is the only possibility of timeout. Can we understand it this way？

ved-rivos commented 1 month ago

Please see section 4.1.2:

In this version of the specification, only ATS.INVAL command is specified to have a timeout.