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riscv-non-isa / riscv-semihosting

https://jira.riscv.org/browse/RVG-39
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Semihosting binary interface description #16

Closed TommyMurphyTM1234 closed 2 months ago

TommyMurphyTM1234 commented 3 months ago

The RISC-V semihosting binary interface consist of a trap instruction sequence

Surely it's a breakpoint instruction sequence?

ilg-ul commented 3 months ago

According to Arm, this is a an instruction that must halt the debugger, something like a breakpoint.

If the debugger supports semihosting, and semihosting is enabled, the debugger must check whether the breakpoint is a regular one or a semihosting breakpoint. In the second case it must process the requested service and resume execution.

So yes, semihosting services are invoked via custom software breakpoints.

avpatel commented 2 months ago

I will update the text to use "breakpoint instruction sequence" instead of "trap instruction sequence"