riscv-non-isa / riscv-semihosting

https://lf-riscv.atlassian.net/browse/RVS-2673
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Listing 2. RISC-V Semihosting Trap Function - why `.balign 16`? #17

Closed TommyMurphyTM1234 closed 4 months ago

TommyMurphyTM1234 commented 5 months ago

.option norvc
  .text
  .balign 16
  .global sys_semihost
  .type sys_semihost @function
sys_semihost:
  slli zero, zero, 0x1f
  ebreak
  srai zero, zero, 0x7
  ret

Why .balign 16?

ilg-ul commented 5 months ago

If .balign 16 means 'align to next 16 byte border', this should ensure that if the sequence occurs right at the end of a virtual memory page it is moved at the beginning of next page.

TommyMurphyTM1234 commented 5 months ago

Thanks @ilg-ul - so the value of 16 comes from the fact that the semihosting instruction sequence is 16 bytes long (4 x 32-bit wide instructions)? Or is it 12 bytes long? Which is the actual authoritative/canonical sequence - this:

slli x0, x0, 0x1f # 0x01f01013 Entry NOP
ebreak # 0x00100073 Break to debugger
srai x0, x0, 7 # 0x40705013 NOP encoding the semihosting call number 7

or this:

slli zero, zero, 0x1f
ebreak
srai zero, zero, 0x7
ret
ilg-ul commented 5 months ago

The constraint is that the entire breakpoint sequence must be present at the same time in memory, so that the debugger can inspect the memory and identify if the call is a semihosting breakpoint.

In this case the 3 instructions must be in the same virtual memory page. 16 is 12 rounded up.

As for the second question, as far as I remember, the ret is not part of the mandatory sequence, which must not be a separate function, it can be a macro inlined in as many places as necessary.

ilg-ul commented 4 months ago

I added a separate post with an example of actual code: https://github.com/riscv-non-isa/riscv-semihosting/issues/20.

avpatel commented 4 months ago

I believe comments from @ilg-ul already explain why .balign 16 is needed hence closing this issue.