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riscv-non-isa / riscv-trace-spec

RISC-V Processor Trace Specification
https://jira.riscv.org/browse/RVG-88
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sec_check optional sideband signal mentioned in RISC-V External Debug Security Extension #105

Closed zhangdujiao closed 4 months ago

zhangdujiao commented 4 months ago
Chatpter 3.2. Trace mentioned: "The extension requires that trace availability from each hart is constrained by default. When Zedsec is supported, the optional sideband signal to trace encoder, sec_check[i] [2], must be implemented for each hart i, and this signal must be reset to 1. " But I didn't see the optional sideband signal: **sec_check**[i] signal from https://github.com/riscv-non-isa/riscv-trace-spec in Chapter 4.2.3..
IainCRobertson commented 4 months ago

This new signal is a very recent proposal, and will require an incremental update to the trace spec. This will require at best a fast-track process and realistically will take many months to complete.

There has been discussion about this on the External Debug Security email list.

From the encoder's point of view, when this signal is high the encoder behaves exactly the same as if the halted input were high. It is recommended that if the encoder does not have this new signal that it be simply ORed into the halted input.

Iain

From: zhangdujiao @.> Sent: 29 April 2024 08:09 To: riscv-non-isa/riscv-trace-spec @.> Cc: Subscribed @.***> Subject: [riscv-non-isa/riscv-trace-spec] sec_check optional sideband signal mentioned in RISC-V External Debug Security Extension (Issue #105)

Chatpter 3.2. Trace mentioned: "The extension requires that trace availability from each hart is constrained by default. When Zedsec is supported, the optional sideband signal to trace encoder, sec_check[i] [2], must be implemented for each hart i, and this signal must be reset to 1. "

But I didn't see the optional sideband signal: sec_check[i] signal from https://github.com/riscv-non-isa/riscv-trace-spec in Chapter 4.2.3..

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zhangdujiao commented 4 months ago

Thanks a lot! That is to say, sec_check sideband signal will be added to the ingress port eventually, and it may takes months to finish.

This will require at best a fast-track process and realistically will take many months to complete.