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riscv-non-isa / riscv-trace-spec

RISC-V Processor Trace Specification
https://jira.riscv.org/browse/RVG-88
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Payload size is limited in 31bytes (248bit), witch is not enough for Format 3 subformat 1 - Trap #114

Closed zhangdujiao closed 3 months ago

zhangdujiao commented 3 months ago

The max size of Format 3 subformat 1 - Trap is 330 bit theoretically. <Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V> limit the payload size in 248 bit. Do we need to send two packets separately?

IainCRobertson commented 3 months ago

I'd be interested to see how you got to 330 bits. But yes, if the payload exceeds 248 bits it would need to be split into 2. There are various ways this could be accommodated, but I don't think it should be necessary as I don't believe any real-world system is going to get anywhere near the 248-bit limit.

Iain

From: zhangdujiao @.> Sent: 05 June 2024 10:08 To: riscv-non-isa/riscv-trace-spec @.> Cc: Subscribed @.***> Subject: Re: [riscv-non-isa/riscv-trace-spec] Payload size is limited in 31bytes (248bit), witch is not enough for Format 3 subformat 1 - Trap (Issue #114)

The max size of Format 3 subformat 1 - Trap is 330 bit theoretically. <Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V> limit the payload size in 248 bit. Do we need to send two packets separately?

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zhangdujiao commented 3 months ago

I'd be interested to see how you got to 330 bits.

For example: Format 3 subformat 1 - Trap " format 2bit subformat 2bit branch 1bit privilege 3bit time 64 bit context 64 bit ecause 64 bit interrupt 1 bit thaddr 1bit address 64bit tval 64bit " The payload size 330bits total. We can put timestamp in ATDATA rather than payload, while the payload is 266 bits then, still larger than 248 bits.

IainCRobertson commented 3 months ago

I have never seen any suggestion that ecause is more than 6 bits wide. Currently any codes > 64 are reserved, and even if this changes at some point the total number of bits might increase to 7 or 8, but not 64 (actually 63, as the MSB of the xcause registers is used for the interrupt bit). If you assume 6 bits for ecause and include the timestamp in the encapsulation rather than in the packet itself the total length is 208.

Splitting across multiple packet is straightforward but not currently standardized. This is something that can be addressed in future if it ever becomes necessary. I don't believe there is any immediate danger of that.

Iain

From: zhangdujiao @.> Sent: 05 June 2024 13:55 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Payload size is limited in 31bytes (248bit), witch is not enough for Format 3 subformat 1 - Trap (Issue #114)

I'd be interested to see how you got to 330 bits.

For example: Format 3 subformat 1 - Trap " format 2bit subformat 2bit branch 1bit privilege 3bit time 64 bit context 64 bit ecause 64 bit interrupt 1 bit thaddr 1bit address 64bit tval 64bit " The payload size 330bits total. We can put timestamp in ATDATA rather than payload, while the payload is 266 bits then, still larger than 248 bits.

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zhangdujiao commented 3 months ago

I have never seen any suggestion that ecause is more than 6 bits wide. Currently any codes > 64 are reserved, and even if this changes at some point the total number of bits might increase to 7 or 8, but not 64 (actually 63, as the MSB of the xcause registers is used for the interrupt bit).

Got it, we need to re-considerate the width of port signals, many thanks Iain.

zhangdujiao commented 3 months ago

the MSB of the xcause registers is used for the interrupt bit

The ingress port signal cause includes the value from ucause/scause/ vscause/mcause, and the MSB of the xcause registers is used for the interrupt bit. So, the whole xcause value should be included in the packet. Otherwise, the decoder cannot determine the cause as an interrupt or an exception, right?

IainCRobertson commented 3 months ago

Yes. But you only need as many bits in ecause as there are defined exception causes. This is currently a max of 6 bits, and in some implementations only 5.

Iain

From: zhangdujiao @.> Sent: 07 June 2024 04:33 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Payload size is limited in 31bytes (248bit), witch is not enough for Format 3 subformat 1 - Trap (Issue #114)

the MSB of the xcause registers is used for the interrupt bit

The ingress port signal cause includes the value from ucause/scause/ vscause/mcause, and the MSB of the xcause registers is used for the interrupt bit. So, the whole xcause value should be included in the packet. Otherwise, the decoder cannot determine the cause as an interrupt or an exception, right?

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zhangdujiao commented 3 months ago

But you only need as many bits in ecause as there are defined exception causes. This is currently a max of 6 bits, and in some implementations only 5.

If only the LSB 6 bits of xcause are contained in packet, instead of all 64 bits, can we determine whether the xcause value indicates an interrupt or an exception cause? Can the interrupt field in Trap packet indicate an interrupt or exception?

IainCRobertson commented 3 months ago

Yes, because the MSB is connected to the 'interrupt' signal in the interface.

Iain

From: zhangdujiao @.> Sent: 07 June 2024 09:01 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Payload size is limited in 31bytes (248bit), witch is not enough for Format 3 subformat 1 - Trap (Issue #114)

But you only need as many bits in ecause as there are defined exception causes. This is currently a max of 6 bits, and in some implementations only 5.

If only the LSB 6 bits of xcause are contained in packet, instead of all 64 bits, can we determine whether the xcause value indicates an interrupt or an exception cause? Can the interrupt field in Trap packet indicate an interrupt or exception?

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zhangdujiao commented 3 months ago

Yes, because the MSB is connected to the 'interrupt' signal in the interface.

Got it! Many thanks!