Target address configuration for trace payload in TE

[zhangdujiao]

We meet a tricky situation in our design...We want to shrink the link and sink components for some reason, area limitation in SoC etc. The encapsulated trace packets are connected to the BUS directly. So, we need to program the routing address inside the TE rather than in SMEM... I know this function is out of the specification of TE. We want to know if you have any suggestion for our specific design. Many thanks!

[IainCRobertson]

Hi there. It's difficult to offer advice based on the short description you have provided, as I know nothing about your SoC. Superficially, the obvious solution would seem to be to include a non-standard memory mapped register that you could use to specify the address. But this seems so obvious that I suspect you would have already considered this...

Iain

From: zhangdujiao @.> Sent: 04 July 2024 07:48 To: riscv-non-isa/riscv-trace-spec @.> Cc: Subscribed @.***> Subject: [riscv-non-isa/riscv-trace-spec] Target address configuration for trace payload in TE (Issue #128)

We meet a tricky situation in our design...We want to shrink the link and sink components for some reason, area limitation in SoC etc. The encapsulated trace packets are connected to the BUS directly. So, we need to program the routing address inside the TE rather than in SMEM... I know this function is out of the specification of TE. We want to know if you have any suggestion for our specific design. Many thanks!

- Reply to this email directly, view it on GitHubhttps://github.com/riscv-non-isa/riscv-trace-spec/issues/128, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ALQOPSU52QNXA5ALUNEVOFLZKTV3XAVCNFSM6AAAAABKK4YOZOVHI2DSMVQWIX3LMV43ASLTON2WKOZSGM4TAMBYGM3DQMY. You are receiving this because you are subscribed to this thread.Message ID: @.**@.>>

[zhangdujiao]

Hi there. It's difficult to offer advice based on the short description you have provided, as I know nothing about your SoC. Superficially, the obvious solution would seem to be to include a non-standard memory mapped register that you could use to specify the address. But this seems so obvious that I suspect you would have already considered this... Iain From: zhangdujiao @.> Sent: 04 July 2024 07:48 To: riscv-non-isa/riscv-trace-spec @.> Cc: Subscribed @.> Subject: [riscv-non-isa/riscv-trace-spec] Target address configuration for trace payload in TE (Issue #128) We meet a tricky situation in our design...We want to shrink the link and sink components for some reason, area limitation in SoC etc. The encapsulated trace packets are connected to the BUS directly. So, we need to program the routing address inside the TE rather than in SMEM... I know this function is out of the specification of TE. We want to know if you have any suggestion for our specific design. Many thanks! - Reply to this email directly, view it on GitHub<#128>, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ALQOPSU52QNXA5ALUNEVOFLZKTV3XAVCNFSM6AAAAABKK4YOZOVHI2DSMVQWIX3LMV43ASLTON2WKOZSGM4TAMBYGM3DQMY. You are receiving this because you are subscribed to this thread.Message ID: @*.**@*.***>>

yes, a non-standard memory mapped register is being considered. The problem may be the commercial debugger may not support this non-standard definition.

[zhangdujiao]

Can I simply think that just integrate the address configuration related registers into the TE? regardless of compatibility problems..

[IainCRobertson]

Why would you not use the RAM Sink register map defined in the Trace Common Control spec for this purpose?

Iain

From: zhangdujiao @.> Sent: 05 July 2024 07:35 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Target address configuration for trace payload in TE (Issue #128)

Can I simply think that just integrate the address configuration related registers into the TE? regardless of compatibility problems..

- Reply to this email directly, view it on GitHubhttps://github.com/riscv-non-isa/riscv-trace-spec/issues/128#issuecomment-2210272150, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ALQOPST6HXCVZILS5LWZA53ZKY5BBAVCNFSM6AAAAABKK4YOZOVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDEMJQGI3TEMJVGA. You are receiving this because you commented.Message ID: @.**@.>>

[zhangdujiao]

yes that's the plan, but the trace32 from Lauterbach may not provide  the support. That's our concern..

发自我的iPhone

------------------ Original ------------------ From: IainCRobertson @.> Date: Fri,Jul 5,2024 3:54 PM To: riscv-non-isa/riscv-trace-spec @.> Cc: zhangdujiao @.>, Author @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Target address configuration fortrace payload in TE (Issue #128)

Why would you not use the RAM Sink register map defined in the Trace Common Control spec for this purpose?

Iain

From: zhangdujiao @.> Sent: 05 July 2024 07:35 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Target address configuration for trace payload in TE (Issue #128)

Can I simply think that just integrate the address configuration related registers into the TE? regardless of compatibility problems..

- Reply to this email directly, view it on GitHub<https://github.com/riscv-non-isa/riscv-trace-spec/issues/128#issuecomment-2210272150&gt;, or unsubscribe<https://github.com/notifications/unsubscribe-auth/ALQOPST6HXCVZILS5LWZA53ZKY5BBAVCNFSM6AAAAABKK4YOZOVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDEMJQGI3TEMJVGA&gt;. You are receiving this because you commented.Message ID: @.**@.>>

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[IainCRobertson]

That’s something you will have to take up with Lauterbach.

Iain

From: zhangdujiao @.> Sent: 05 July 2024 12:37 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Target address configuration for trace payload in TE (Issue #128)

yes that's the plan, but the trace32 from Lauterbach may not provide  the support. That's our concern..

发自我的iPhone

------------------ Original ------------------ From: IainCRobertson @.&gt<mailto:@.&gt>; Date: Fri,Jul 5,2024 3:54 PM To: riscv-non-isa/riscv-trace-spec @.&gt<mailto:@.&gt>; Cc: zhangdujiao @.&gt<mailto:@.&gt>;, Author @.&gt<mailto:@.&gt>; Subject: Re: [riscv-non-isa/riscv-trace-spec] Target address configuration fortrace payload in TE (Issue #128)

Why would you not use the RAM Sink register map defined in the Trace Common Control spec for this purpose?

Iain

From: zhangdujiao @.&gt<mailto:@.&gt>; Sent: 05 July 2024 07:35 To: riscv-non-isa/riscv-trace-spec @.&gt<mailto:@.&gt>; Cc: Robertson, Iain (DI SW ICS TST RD EAH) @.&gt<mailto:@.&gt>;; Comment @.&gt<mailto:@.&gt>; Subject: Re: [riscv-non-isa/riscv-trace-spec] Target address configuration for trace payload in TE (Issue #128)

Can I simply think that just integrate the address configuration related registers into the TE? regardless of compatibility problems..

- Reply to this email directly, view it on GitHub<https://github.com/riscv-non-isa/riscv-trace-spec/issues/128#issuecomment-2210272150&gt;, or unsubscribe<https://github.com/notifications/unsubscribe-auth/ALQOPST6HXCVZILS5LWZA53ZKY5BBAVCNFSM6AAAAABKK4YOZOVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDEMJQGI3TEMJVGA&gt;. You are receiving this because you commented.Message ID: @.**@.>>

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[zhangdujiao]

yes, thanks Iain