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riscv-non-isa / riscv-trace-spec

RISC-V Processor Trace Specification
https://jira.riscv.org/browse/RVG-88
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Trace mode configuration #131

Closed zhangdujiao closed 4 months ago

zhangdujiao commented 4 months ago

For the trace mode, like delta address mode, full address, implicit exception mode, etc.. Can we configure multiple Trace Modes at the same time? or only one mode can be applied simultaneously..

IainCRobertson commented 4 months ago

Yes, they are orthogonal and can be enabled in any combination.

Iain

From: zhangdujiao @.> Sent: 23 July 2024 14:31 To: riscv-non-isa/riscv-trace-spec @.> Cc: Subscribed @.***> Subject: [riscv-non-isa/riscv-trace-spec] Trace mode configuration (Issue #131)

For the trace mode, like delta address mode, full address, implicit exception mode, etc.. Can we configure multiple Trace Modes at the same time? or only one mode can be applied simultaneously..

- Reply to this email directly, view it on GitHubhttps://github.com/riscv-non-isa/riscv-trace-spec/issues/131, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ALQOPSU4GJOXCBCYGD7LXRDZNZLJDAVCNFSM6AAAAABLKOJDT6VHI2DSMVQWIX3LMV43ASLTON2WKOZSGQZDKMRSHE2DSNQ. You are receiving this because you are subscribed to this thread.Message ID: @.**@.>>

zhangdujiao commented 4 months ago

Yes, they are orthogonal and can be enabled in any combination.

But the ioption field only reports 1 operation mode in one support packet, right? What if TE in running in two mode together? How ioption can report more operation mode?

IainCRobertson commented 4 months ago

The ioption field should be a bit vector with 1 bit for each option. In that way any number can be indicated simultaneously.

Iain

From: zhangdujiao @.> Sent: 24 July 2024 01:53 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS DDCP TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Trace mode configuration (Issue #131)

Yes, they are orthogonal and can be enabled in any combination.

But the ioption field only reports 1 operation mode in one support packet, right? What if TE in running in two mode together? How ioption can report more operation mode?

- Reply to this email directly, view it on GitHubhttps://github.com/riscv-non-isa/riscv-trace-spec/issues/131#issuecomment-2246652162, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ALQOPSTYO5USUGY2BBBORZLZN33ITAVCNFSM6AAAAABLKOJDT6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDENBWGY2TEMJWGI. You are receiving this because you commented.Message ID: @.**@.>>

zhangdujiao commented 4 months ago

The ioption field should be a bit vector with 1 bit for each option. In that way any number can be indicated simultaneously. Iain From: zhangdujiao @.> Sent: 24 July 2024 01:53 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS DDCP TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Trace mode configuration (Issue #131) Yes, they are orthogonal and can be enabled in any combination. But the ioption field only reports 1 operation mode in one support packet, right? What if TE in running in two mode together? How ioption can report more operation mode? - Reply to this email directly, view it on GitHub<#131 (comment)>, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ALQOPSTYO5USUGY2BBBORZLZN33ITAVCNFSM6AAAAABLKOJDT6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDENBWGY2TEMJWGI. You are receiving this because you commented.Message ID: @.**@.>>

thanks, there are 7 modes in Chapter 3.2 totally. The "delta address mode" and "full address mode" are mutually exclusive. Do we need to use 1 bit to represent these two modes? like, 0: delta mode, 1: full mode. For the implicit return mode, there are there application methods totally: simple counting, partial address compare, full address compare. Do we need to list them all in the ioption field? Thanks

IainCRobertson commented 4 months ago

See inline...

Iain

From: zhangdujiao @.> Sent: 25 July 2024 04:23 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS DDCP TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Trace mode configuration (Issue #131)

The ioption field should be a bit vector with 1 bit for each option. In that way any number can be indicated simultaneously. Iain From: zhangdujiao @.> Sent: 24 July 2024 01:53 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS DDCP TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Trace mode configuration (Issue #131https://github.com/riscv-non-isa/riscv-trace-spec/issues/131) Yes, they are orthogonal and can be enabled in any combination. But the ioption field only reports 1 operation mode in one support packet, right? What if TE in running in two mode together? How ioption can report more operation mode? - Reply to this email directly, view it on GitHub<#131 (comment)https://github.com/riscv-non-isa/riscv-trace-spec/issues/131#issuecomment-2246652162>, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ALQOPSTYO5USUGY2BBBORZLZN33ITAVCNFSM6AAAAABLKOJDT6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDENBWGY2TEMJWGI. You are receiving this because you commented.Message ID: @.@.>>

thanks, there are 7 modes in Chapter 3.2 totally. The "delta address mode" and "full address mode" are mutually exclusive. Do we need to use 1 bit to represent these two modes? like, 0: delta mode, 1: full mode.

[Iain] Yes, just 1 bit.

For the implicit return mode, there are there application methods totally: simple counting, partial address compare, full address compare. Do we need to list them all in the ioption field?

[Iain] There is no mention of full vs partial address compare in the E-Trace spec, so I'm not sure what you're referring to here. However, I'd expect only a single bit for implicit return mode. If the hardware has implemented a return stack then I'd expect this to always be used, and the simple counting method to be used only when there is no return stack. If the hardware has implemented a return stack then the return_stack_size_p discoverable parameter will be non-zero.

Thanks

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