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riscv-non-isa / riscv-trace-spec

RISC-V Processor Trace Specification
https://jira.riscv.org/browse/RVG-88
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The field width of branch_map in format 1 #133

Closed zhangdujiao closed 1 month ago

zhangdujiao commented 1 month ago

Can the width of branch_map be fixed at 31bit, rather than determined by branches value, since the latter will need lots of registers for implementation.

IainCRobertson commented 1 month ago

No, this is not possible (at least, not whilst remaining compliant to the E-Trace standard).

In our implementation this doesn't cost any registers, but it does require muxes to correctly align the upper part of the trace packet payload. Whilst the approach you suggest would reduce the muxing cost, it would significantly impact the encoding efficiency.

Iain

From: zhangdujiao @.> Sent: 04 August 2024 04:46 To: riscv-non-isa/riscv-trace-spec @.> Cc: Subscribed @.***> Subject: [riscv-non-isa/riscv-trace-spec] The field width of branch_map in format 1 (Issue #133)

Can the width of branch_map be fixed at 31bit, rather than determined by branches value, since the latter will need lots of registers for implementation.

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