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riscv-non-isa / riscv-trace-spec

RISC-V Processor Trace Specification
https://jira.riscv.org/browse/RVG-88
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Roles of resync counter updating in different trTeControl.trTeInstSyncMode #168

Closed zhangdujiao closed 1 month ago

zhangdujiao commented 1 month ago

There are three SyncModes totally 1: Count trace messages/packets 2: Count hart clock cycles 3: Count instruction 16-bit half-words For the 1st "Count trace messages/packets", whether the update time point is before or after packet sending? For the "Count instruction 16-bit half-words", whether to update the counter only when the inst. block is qualified? or update the counter, no matter whether it is qualified? For the "Count hart clock cycles", whether the counter update is only required when trace on (trteactive && trteenable && trtetracing && qualified) or there is no precondition?

Many thanks!

IainCRobertson commented 1 month ago

See inline...

Iain

From: zhangdujiao @.> Sent: 28 October 2024 06:00 To: riscv-non-isa/riscv-trace-spec @.> Cc: Subscribed @.***> Subject: [riscv-non-isa/riscv-trace-spec] Roles of resync counter updating in different trTeControl.trTeInstSyncMode (Issue #168)

There are three SyncModes totally 1: Count trace messages/packets 2: Count hart clock cycles 3: Count instruction 16-bit half-words For the 1st "Count trace messages/packets", whether the update time point is before or after packet sending?

[Iain] After. This is why the algorithm flow chart shows format 0/1/2 sent when the counter equals the threshold, and the sync sent one message later when it exceeds the threshold.

For the "Count instruction 16-bit half-words", whether to update the counter only when the inst. block is qualified? or update the counter, no matter whether it is qualified?

[Iain] This should update with all the half-words retired in a cycle. So for example, if you have an encoder with 2 blocks you should sum iretires for the 2 blocks - this will be the total number of half-words retired in that cycle.

For the "Count hart clock cycles", whether the counter update is only required when trace on (trteactive && trteenable && trtetracing && qualified) or there is no precondition?

[Iain] Yes. No point sending sync messages when trace is off. Same is true for counting half-words.

Many thanks!

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zhangdujiao commented 1 month ago

This should update with all the half-words retired in a cycle. So for example, if you have an encoder with 2 blocks you should sum iretires for the 2 blocks - this will be the total number of half-words retired in that cycle.

We should count all these two retired isnt. blks, no matter whether it is qualified, right?

IainCRobertson commented 1 month ago

You should only count instructions that are traced. If any instructions retiring in a cycle qualify, all the instructions retired in that cycle will be traced. The whole point of the resync mechanism is to ensure Sync packets are generated at regular intervals in the trace packet stream.

Iain

From: zhangdujiao @.> Sent: 29 October 2024 03:01 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW EDA DDCP TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Roles of resync counter updating in different trTeControl.trTeInstSyncMode (Issue #168)

This should update with all the half-words retired in a cycle. So for example, if you have an encoder with 2 blocks you should sum iretires for the 2 blocks - this will be the total number of half-words retired in that cycle.

We should count all these two retired isnt. blks, no matter whether it is qualified, right?

- Reply to this email directly, view it on GitHubhttps://github.com/riscv-non-isa/riscv-trace-spec/issues/168#issuecomment-2443096457, or unsubscribehttps://github.com/notifications/unsubscribe-auth/ALQOPSTO7PC4SJHPMMQLRRTZ5326DAVCNFSM6AAAAABQWU2TDWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDINBTGA4TMNBVG4. You are receiving this because you commented.Message ID: @.**@.>>

zhangdujiao commented 1 month ago

The whole point of the resync mechanism is to ensure Sync packets are generated at regular intervals in the trace packet stream.

OK I get it! Also, for "Count hart clock cycles" mode, only the clock cycles under the trace_on condition (qualified==1) are counted, right?

IainCRobertson commented 1 month ago

Yes, exactly.

Iain

From: zhangdujiao @.> Sent: 29 October 2024 09:27 To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW EDA DDCP TST RD EAH) @.>; Comment @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] Roles of resync counter updating in different trTeControl.trTeInstSyncMode (Issue #168)

The whole point of the resync mechanism is to ensure Sync packets are generated at regular intervals in the trace packet stream.

OK I get it! Also, for "Count hart clock cycles" mode, only the clock cycles under the trace_on condition (qualified==1) are counted, right?

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