Addresses written on 64 bits in Reference Flow

While analyzing annotated encoder output generated by Reference Flow I noticed that all differential addresses are written (and probably stored) as 64-bit values. In most cases that makes no difference due to the compression applied to packets, but in some cases (e.g. when notify, updiscon or irreport fields are different from address MSB in format 2 packets) result packets are wrong. Here are some examples (names of test are also visible at the top of the screenshots):

In the above image you can see that format 2 packet (line 7223) contains such an address and notify field is 1, so MSBs of adress cannot be compressed out.

Here is another example, this time posistive difference value written on 64 bits (line 707): This time irreport and updiscon fields are non-zero, so redundant zeroes stay in packet.

Files shown above were generated by commands: scripts/run_regression.sh vvadd -t itype3_basic --annotate and scripts/run_regression.sh hello_world -t itype3_basic --annotate ran from referenceFlow directory

Also the question is why decoder has no issue with it?

Bohdan, Apologies for taking so long to reply - I was on vacation and this got lost in the backlog.

I don't see an issue here. The two cases you highlighted (on lines 7223 and 707) decode as follows. I'm laying out the packets from right to left:

03 ff ff ff ff ff ff fb fa fc 00 00 00 00 00 00 18 d6

The address field is 63 bits, spanning bits 64:2 of the payload. Shift left (i.e. x2) to convert to a byte address differential. The resulting byte address differentials are -0x204 and 0xc6a respectively.

The high order bits are

65: notify bit. Same value as address MSB, so decodes as logically false 66: updiscon bit. Opposite value to notify, so decodes as logically true 67: irreport bit. Same value as updiscon, so decodes as logically false.

Iain

From: Bohdan Shveida @.> Sent: Wednesday, October 4, 2023 9:59 AM To: riscv-non-isa/riscv-trace-spec @.> Cc: Subscribed @.***> Subject: [riscv-non-isa/riscv-trace-spec] Addresses written on 64 bits in Reference Flow (Issue #87)

[1]https://user-images.githubusercontent.com/48486672/272277042-2f94e7c3-17b1-4d37-bf39-299e45edec12.png In the above image you can see that format 2 packet (line 7223) contains such an address and notify field is 1, so MSBs of adress cannot be compressed out.

Here is another example, this time posistive difference value written on 64 bits (line 707): [2]https://user-images.githubusercontent.com/48486672/272281988-3bc0c12f-41cc-4b88-9da2-17a390627c8b.png This time irreport and updiscon fields are non-zero, so redundant zeroes stay in packet.

Files shown above were generated by commands: scripts/run_regression.sh vvadd -t itype3_basic --annotate and scripts/run_regression.sh hello_world -t itype3_basic --annotate ran from referenceFlow directory

Also the question is why decoder has no issue with it?

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riscv-non-isa / riscv-trace-spec

Addresses written on 64 bits in Reference Flow #87