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riscv-non-isa / riscv-trace-spec

RISC-V Processor Trace Specification
https://jira.riscv.org/browse/RVG-88
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A vector of sideband signals to inform the trace output being stopped #98

Open AoteJin opened 4 months ago

AoteJin commented 4 months ago

Based on discussion on external debug security TG meeting, adding another bit alongside halted signal to bundle a vector is the desired way to inform the trace to stop output due to different reasons. The reserved encoding is for futural extension.

[new_bit, halted] Tracing? Stop reason
00 Yes n/a
01 No entering Debug Mode
10 No due to security rules
11 No reserved for future
IainCRobertson commented 4 months ago

I propose we call this signal ''notrace".

bcstrongx commented 2 months ago

Yeah, seems like bit 0 shouldn't be called halted anymore, since for the reserved 0b11 case we may not be halted. I might lean towards "traceinh[1:0]", but don't care that much.

One trick with this is that an implementation can't simply connect bit 0 to halted and bit 1 to security check failure. Otherwise the encoder could see 0b11 when the hart is both halted and security checks fail (e.g., we halted in M-mode but trace is not allowed in M-mode). The table above is clear enough, but the external debug spec probably needs clarification here.

IainCRobertson commented 2 months ago

Agree - we need a new name for the new vector, not a new signal that has an encoded meaning with halted. That’s a recipe for screw ups.

I guess you’re thinking “trace inhibit”? I don’t think we need “trace” in the name of the ingress port signal - they’re all for trace! So we could just go with “inhibit”? I prefer that to traceinh as it’s not so obvious to the casual reader what “inh” means.

From: Beeman Strong @.> Sent: Tuesday, June 4, 2024 6:14:25 PM To: riscv-non-isa/riscv-trace-spec @.> Cc: Robertson, Iain (DI SW ICS TST RD EAH) @.>; Assign @.> Subject: Re: [riscv-non-isa/riscv-trace-spec] A vector of sideband signals to inform the trace output being stopped (Issue #98)

Yeah, seems like bit 0 shouldn't be called halted anymore, since for the reserved 0b11 case we may not be halted. I might lean towards "traceinh[1:0]", but don't care that much.

One trick with this is that an implementation can't simply connect bit 0 to halted and bit 1 to security check failure. Otherwise the encoder could see 0b11 when the hart is both halted and security checks fail (e.g., we halted in M-mode but trace is not allowed in M-mode). The table above is clear enough, but the external debug spec probably needs clarification here.

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bcstrongx commented 2 months ago

good point, inhibit works