riscv-non-isa / riscv-trace-spec

RISC-V Processor Trace Specification
https://jira.riscv.org/browse/RVG-88
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Make priority of trace-on and trace-off explicit #99

Open IainCRobertson opened 5 months ago

IainCRobertson commented 5 months ago

The behaviour when trace-off and trace-on triggers occur on consecutive instructions is not spelt out explicitly, but should be: tracing continues unimpeded. See also https://github.com/riscv-non-isa/riscv-external-debug-security/issues/11 for discussion on this.