Closed camel-cdr closed 1 year ago
You can currently do this with a sequence of calls to the "vector insertion intrinsics", e.g., __riscv_vset_v_i8m1_i8m8
. Although this is more verbose than the single intrinsic you request, it is also more flexible.
Ah, true. This works, thanks.
Hi, would it be possible to add intrinsics akin to
vuint8m8_t __riscv_vreinterprete_8xu8m1(vuint8m1_t a, vuint8m1_t b, vuint8m1_t c, vuint8m1_t d, vuint8m1_t e, vuint8m1_t f, vuint8m1_t g, vuint8m1_t h)
.This above would force the compiler to allocate the LMUL=1 registers a to h in a single LMUL=8 register. E.g.
a=v0, b=v1, ..., h=v7
.