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riscv-non-isa / rvv-intrinsic-doc

https://jira.riscv.org/browse/RVG-153
BSD 3-Clause "New" or "Revised" License
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Remove overloaded variants of masked vector load instruction intrinsics (seg and non-seg) #267

Closed eopXD closed 12 months ago

eopXD commented 1 year ago

The intrinsics contain all scalar parameters and by the limitation of the C language we are not able to implement overloaded variants of them in the compiler.

This was an oversight in the specification. The LLVM test suite passes the clang front-end test case because the test case only checks if LLVM IR can be generated. In fact, the test cases can not be compiled successfully.

dzaima commented 1 year ago

While unmasked loads cannot be overloaded, masked ones technically can (and, it seems, are handled correctly by both gcc and clang - https://godbolt.org/z/Gbe3GaqP5), due to the mask/maskedoff argument type effectively including LMUL information. Granted, this is pretty weird, and without maskedoff it relies on the pointer element type, and the clang error message for the unmasked case seems to be slightly broken. (I don't have much of an opinion on whether these should be kept or removed)

eopXD commented 12 months ago

@dzaima Thank you for checking. I intended to remove those mis-printed ones and not the ones we already support. I will update the patch.

eopXD commented 12 months ago

Hmmm, after compiling with RISC-V headers I realized that this PR is totally redundant. We do have the supported prototypes printed, and un-supported ones omitted. Sorry for the noise.