riscv-non-isa / rvv-intrinsic-doc

https://jira.riscv.org/browse/RVG-153
BSD 3-Clause "New" or "Revised" License
277 stars 88 forks source link

Simple questions about inline assembly in vmv.x.s instruction #314

Closed Rhythmicc closed 4 months ago

Rhythmicc commented 4 months ago

I've composed an uncomplicated C program that implements the vmv.x.s instruction via both direct register specification and compiler register specification. However, I've observed that while the program with direct register specification compiles successfully, the one with compiler register specification triggers an error. Could this be due to an incorrect method of invocation on my part? If so, how should I amend it?

#include <stdio.h>
#include <stdint.h>
#include <riscv_vector.h>

int main(int argc, char **argv) {
    int64_t tv[4] = {1,0,1,0};

    vint64m1_t task = __riscv_vle64_v_i64m1(tv, 4);
    int64_t scalarValue = 0;

    __asm__ volatile(
        "vmv.x.s %0, v0"
        : "=r"(scalarValue)
        :
        : 
    );

    __asm__ volatile(
        "vmv.x.s %0, %1"
        : "=r"(scalarValue)
        : "v"(task)
        : 
    );

    printf("Scalar value: %lld\n", scalarValue);

    return 0;
}

compiler error:

main.c:19:5: error: impossible constraint in 'asm'
19 |     __asm__ volatile(
|     ^~~~~~~
topperc commented 4 months ago

The constraint for vector register is "vr" not "v"

Rhythmicc commented 4 months ago

Thanks!