ta,ma reduction destination with vl=0

[dzaima]

riscv-isa-manual specifies that vector reduction operations with vl=0 don't update their destination register at all.

Tail-agnostic mask-agnostic reduction intrinsics (e.g. __riscv_vredand_vs_i32m2_i32m1) do not provide a configurable initial destination value, meaning that they essentially return an arbitrary result when vl=0, whereas it could be useful to be able to provide a custom one. Namely, the manual notes that using the same source & destination register can provide a guarantee that the destination always gives the expected reduction result, but there's no way to do this with intrinsics.

The best option as-is with intrinsics is to use a _tu reduction, but this clearly has a downside.

(not a super-important issue considering that vl=0 is a pain by itself (initializing said initial scalar argument requires some vl>0 at some point anyway), but worth noting nonetheless)

[nick-knight]

Agreed. We discussed this internally at SiFive two years ago, here were my notes: https://gist.github.com/nick-knight/b02a16c35d743a672f1c284b0e8b9092 (I don't think there is anything sensitive to SiFive so I'm happy to share the URL here.)