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riscv-non-isa / server-soc

The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
https://jira.riscv.org/browse/RVG-58
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PCIe Integration: do we need a rule about byte enable handling #23

Closed andreiw closed 11 months ago

andreiw commented 11 months ago

See https://developer.arm.com/documentation/den0029/latest

RS_PCIe_01: The system must support the translation of PE writes with all byte enable patterns to PCIe write requests. The translation must be done in compliance with PCIe byte enable rules.

ved-rivos commented 11 months ago

The ECM_010 requires the SoC to support naturally aligned 1/2/4 byte writes. Further MMS_030 require supporting all aligned and unaligned access sizes that can be generated by RISC-V application processor harts or endpoints.

ved-rivos commented 11 months ago

Updated in https://github.com/riscv-non-isa/server-soc/pull/26/commits/ee1361d9b4680a6729b65b25380635ca48bc1ff0 and https://github.com/riscv-non-isa/server-soc/pull/26/commits/220a1b9800c8067be2b7a5182ef03f881e66311e

andreiw commented 11 months ago

Lgtm