riscv-non-isa / tg-nexus-trace

RISC-V Nexus Trace TG documentation and reference code
https://jira.riscv.org/browse/RVG-96
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Can SRAM and SMEM sink be regarded as ETF and ETR in coresight, respectively? #60

Closed zhangdujiao closed 5 months ago

mipsrobert commented 5 months ago

In general we want to avoid using Arm terms directly in the spec😃.

Not exactly. SMEM is ETR what means routing (R) trace to system bus. SRAM is more like ETB. ETF can be a module which supports both SRAM and SMEM modes. Internal SRAM may be used as a destination (if working in SRAM) mode, but it can be used as a FIFO (EFT) in SMEM mode.

zhangdujiao commented 5 months ago

thanks! got it