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riscv-ovpsim / imperas-riscv-tests

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Compliance of Swerv EH1 Core #17

Open YeuzhiHere opened 2 years ago

YeuzhiHere commented 2 years ago

I want to do compliance test for Swerv EH1 Core. Can I do it using riscvOVPsim. Please guide.

Regards

Imperas commented 2 years ago

The Imperas architectural validation tests can be used for testing simulators, models, fpga, RTL, or chips. The test and simulator are pretty simple to set up.

The riscvOVPsim simulator can run the tests and generate the signature files and can be used in different test environments. It has been used with many different RISC-V processors and SweRV will not be different.

Have you already cloned the git repo, got an appropriate RISC-V assembler tool chain, and have you run the tests as cloned? The instructions for this are in this repo.

When you have that working, then we can address your questions, can you explain a little more what you are looking for. What Verilog simulator are you using, what version of SweRV? etc etc.

Simon

YeuzhiHere commented 2 years ago

Ok I will try and will let you know.