Closed i4kimura closed 6 years ago
Codegen for atomics aren't implemented yet in the llvm backend. It should be disabled through "max-atomic-width": 0,
in riscv32-unknown-none.json
. Have you by any chance modified it?
NOTE: The quickstart example doesn't work out of the box. It needs to clear the pending gpio interrupt in the interrupt handler and also see dvc94ch/hifive#2
Thank you for your support.
After solving https://github.com/dvc94ch/riscv-rust-toolchain/issues/4, I confirmed make build
can make RISC-V binary.
Hi,
I built riscv-rust-toolchain on Ubuntu 17.10 and tried to build riscv-rust-quickstart: I modified
RISCV_RUST_TOOLCHAIN
in evn.sh and hitmake build
but I got following error:with
--verbose
Could you give me some advice to solve this?