compile error with riscv-rust-toolchain

[i4kimura]

Hi,

I built riscv-rust-toolchain on Ubuntu 17.10 and tried to build riscv-rust-quickstart: I modified RISCV_RUST_TOOLCHAIN in evn.sh and hit make build but I got following error:

$ make build
xargo build --target riscv32-unknown-none
   Compiling core v0.0.0 (file:///home/msyksphinz/work/riscv-rust-toolchain/rust/src/libcore)
LLVM ERROR: Cannot select: t107: i32,ch = AtomicLoad<Volatile LD1[%15]> t46, t2
  t2: i32,ch = CopyFromReg t0, Register:i32 %vreg9
    t1: i32 = Register %vreg9
In function: _ZN67_$LT$core..sync..atomic..AtomicBool$u20$as$u20$core..fmt..Debug$GT$3fmt17hc6a29f4acb3c894eE
error: Could not compile `core`.

To learn more, run the command again with --verbose.
error: `"cargo" "build" "--release" "--manifest-path" "/tmp/xargo.WZzehUAByIZ6/Cargo.toml" "--target" "riscv32-unknown-none" "-p" "alloc"` failed with exit code: Some(101)
note: run with `RUST_BACKTRACE=1` for a backtrace
Makefile:5: recipe for target 'build' failed
make: *** [build] Error 1

with --verbose

$ xargo build --verbose --target riscv32-unknown-none
+ "rustc" "--print" "sysroot"
+ "rustc" "--print" "target-list"
+ "cargo" "build" "--release" "--manifest-path" "/tmp/xargo.84aDJjh1M7p1/Cargo.toml" "--target" "riscv32-unknown-none" "-v" "-p" "alloc"
   Compiling core v0.0.0 (file:///home/msyksphinz/work/riscv-rust-toolchain/rust/src/libcore)
     Running `rustc --crate-name core /home/msyksphinz/work/riscv-rust-toolchain/rust/src/libcore/lib.rs --crate-type lib --emit=dep-info,link -C opt-level=3 -C metadata=4fff07133b7934d6 -C extra-filename=-4fff07133b7934d6 --out-dir /tmp/xargo.84aDJjh1M7p1/target/riscv32-unknown-none/release/deps --target riscv32-unknown-none -L dependency=/tmp/xargo.84aDJjh1M7p1/target/riscv32-unknown-none/release/deps -L dependency=/tmp/xargo.84aDJjh1M7p1/target/release/deps -C link-arg=-Tlink.x -C linker=riscv32-unknown-elf-ld --sysroot /home/msyksphinz/work/riscv-rust-toolchain/build/xargo -Z force-unstable-if-unmarked`
LLVM ERROR: Cannot select: t107: i32,ch = AtomicLoad<Volatile LD1[%15]> t46, t2
  t2: i32,ch = CopyFromReg t0, Register:i32 %vreg9
    t1: i32 = Register %vreg9
In function: _ZN67_$LT$core..sync..atomic..AtomicBool$u20$as$u20$core..fmt..Debug$GT$3fmt17hc6a29f4acb3c894eE
error: Could not compile `core`.

Could you give me some advice to solve this?

[dvc94ch]

Codegen for atomics aren't implemented yet in the llvm backend. It should be disabled through "max-atomic-width": 0, in riscv32-unknown-none.json. Have you by any chance modified it?

NOTE: The quickstart example doesn't work out of the box. It needs to clear the pending gpio interrupt in the interrupt handler and also see dvc94ch/hifive#2

[i4kimura]

Thank you for your support. After solving https://github.com/dvc94ch/riscv-rust-toolchain/issues/4, I confirmed make build can make RISC-V binary.