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riscv-software-src / riscof

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Connect Riscof to SweRV EH2 core #10

Closed SyoAnd closed 3 years ago

SyoAnd commented 3 years ago

How would I use riscof to validate the SweRV RH2 core from Western Digital? https://github.com/chipsalliance/Cores-SweRV-EH2

I expect that I have to use an EDA tool, like Cadence Xcelium, but I have no idea how to connect riscof to it. Maybe I am blind, but the documentation mentions the ability to validate RTL code many times but does never state how to do it.

Currently, I have a working Riscof setup with spike and sail_model.

pawks commented 3 years ago

Anything which can be run via the command line and doesn't need a GUI to be used can be used with riscof. The plugins for SAIL and SPIKE write out Makefiles at riscof_work/Makefile.<name> which are then used to actually run the tests on the core and generate signatures. Something similar can be done for any RTL/simulator.

The readme in the SweRV repository shows that there is support for generating a verilator simulator of the core. Verilator is a free to use tool and can generate a binary for the RTL, which can be used to run programs. You will have to write a custom plugin for the same. This guide documents the architecture of the plugins and what each function in the plugin should do. You can find a few example plugins here. You will also need to define the DUT specific macros in a custom header file and a custom linker script based on the RTL. The list of DUT specific macros and their intended functionality can be found in the test spec format (here and here). You will also need yaml files which describe the configuration of the core. Currently test selection is only based on the ISA of the core for the most part and you can find the documentation for writing the yaml files here. The yaml files for each of the example plugins are present in their respective folders(example).

The plugin for the cClass core from SHAKTI, IITM can be found here and can be used for inspiration. Please note that the plugin was for an older version of riscof and has not been updated to accommodate the recent changes. Hence it might not work with the latest version of riscof.

neelgala commented 3 years ago

You can also refer to the chromite-core plugin here which should work with the latest riscof version. It has a readme and the plugin files are also well commented. It should provide a decent starting point.

haseebazaz-10xe commented 3 years ago

I am integrating SweRV-el2 to run with riscof environment taking chromite as reference. I created a directory in riscof-plugins with all the files creating according to SweRV-el2 like config.ini, env, isa, platform and python file too and in core I was also able to create executable but when run core with riscof environment I get error that some memory file is missing. I also looked into chromite and see that there is boot.mem file too which I don't see in SweRV directory and I don't know how to generate boot.mem file in case of SweRV. As in case of chromite there is .dts file which is used to generate boot.mem but I don't see any in case of SweRV. What should I do now?

pawks commented 3 years ago

I am integrating SweRV-el2 to run with riscof environment taking chromite as reference. I created a directory in riscof-plugins with all the files creating according to SweRV-el2 like config.ini, env, isa, platform and python file too and in core I was also able to create executable but when run core with riscof environment I get error that some memory file is missing. I also looked into chromite and see that there is boot.mem file too which I don't see in SweRV directory and I don't know how to generate boot.mem file in case of SweRV. As in case of chromite there is .dts file which is used to generate boot.mem but I don't see any in case of SweRV. What should I do now?

The SweRV repo might be a better to place to ask this question. I had a quick glance over at the makefile in the repository and looks like the SweRV core does not require a boot.mem file. The compiled binary can be directly executed on the core.