Currently RVMODEL_SET_MSW_INT, RVMODEL_CLEAR_MSW_INT, RVMODEL_SET_MTIMER_INT, RVMODEL_CLEAR_MTIMER_INT aren't used by any architecture tests. This pull updates their functionality to work with sail/spike CLINT models so future interrupt tests can use the macros to set and clear interrupts.
update model_test.h RVMODLE MSW/MTIMER macros to match https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/model_test.h
Currently RVMODEL_SET_MSW_INT, RVMODEL_CLEAR_MSW_INT, RVMODEL_SET_MTIMER_INT, RVMODEL_CLEAR_MTIMER_INT aren't used by any architecture tests. This pull updates their functionality to work with sail/spike CLINT models so future interrupt tests can use the macros to set and clear interrupts.