search

riscv-software-src / riscof

BSD 3-Clause "New" or "Revised" License
63 stars 40 forks source link

Documentation on how to create the test-bench for RISCOF #120

Closed julienissuts closed 1 month ago

julienissuts commented 1 month ago

Hello everyone, I read your doc about how to build your model plugin. But I couldn't find any description of how the test-bench should be build. I don't know what my test-bench should do and what I need to integrate (like a memory for the instructions etc.). Do you have some information about this or do I have to find it out by investigating other test-benches, like from NeoRV32 or SERV et. ?

Thank you and Best regards, Julien

quswarabid commented 1 month ago

Your plugin have only one responsibilities, after being setup correctly: be able to run a test by calling the right command when the test (name/path) is passed to it.

And your test-bench should be able to dump the signature region onto a file that will then be read by riscof to compare the signatures after all the tests are completely ran.

Go through the riscof's spike plugin (riscof/spike/riscof_spike.py) to understand this. Then run riscof setup --dutname=any_name_here and edit the content of folder any_name_here created from template.

julienissuts commented 1 month ago

I've reviewed the Spike RISCOF plugin documentation and it seems to match the official RISCOF documentation. I understand what the plugin does; however, I'm facing challenges in creating a test-bench for my processor to interface with the RISCOF environment. The documentation mentions that for an RTL-based DUT, I should point to the final binary executable of the test-bench produced by a simulator (like Verilator, VCS, Incisive, etc.).

I am currently trying to conduct the compliance tests for the Ibex processor using the RISCOF framework, but I am unsure how to create a suitable test-bench for the Ibex that works with RISCOF. Could you provide detailed steps or examples on how to set up this test-bench?

julienissuts commented 1 month ago

I think I have to create something similar like the test-bench for the NeoRV32 which I found here https://github.com/stnolting/neorv32-riscof/blob/main/sim/neorv32_riscof_tb.vhd

But I was wondering if you have any specific guide to create such a test-bench

quswarabid commented 1 month ago

A final binary means a command that takes file name as an input and whatever it does, does but also dumps the signature region.

I can share an example where ARA is used.

  1. Code Example (link)
  2. Relevant branch on 10xEngineers fork of Pulp-Platform's ARA (link)
julienissuts commented 1 month ago

Hmm okay I think I get it now. I will investigate the links you sent me, thanks a lot for the help it was really useful.

Best regards Julien