SPIKE DUT failing to simulate after following quickstart guide

[Don-Haugaard]

Hi,

I have followed your quickstart guide to setup and run RISCOF (version 1.23) with Spike as DUT, but ran into issues as RISCOF fails to compile two tests (riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S, riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsw-align-01.S). These tests are put into the generated test list by the suggested "riscof testlist" command. I have installed the RISCV-GNU toolchain and plugin models according to the quickstart guide, so they should be the correct version.

The error messages I get when running "riscof run --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env" are:

riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S: Assembler messages: riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:37: Error: unrecognized opcode flw f18,0x200(x26)' riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:37: Error: unrecognized opcodefsreg f18,0(x15)' (...) riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:161: Error: unrecognized opcode fsreg f16,128(x15)' riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:165: Error: unrecognized opcodeflw f2,-0x800(x12)' riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:165: Error: unrecognized opcode `fsreg f2,136(x15)'

When I peek in the Makefile at the failing target I see the following command for the flw test:

TARGET27 : @cd (...)/riscoftest/riscof_work/rv32i_m/F/src/flw-align-01.S/dut; riscv32-unknown-elf-gcc -march=rv32i -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g -T (...)/riscoftest/spike/env/link.ld -I (...)/riscoftest/spike/env/ -I (...)/riscoftest/riscv-arch-test/riscv-test-suite/env (...)/riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S -o my.elf -DTEST_CASE_1=True -DXLEN=32 -mabi=ilp32 ; spike --isa=rv32imc +signature=(...)/riscoftest/riscof_work/rv32i_m/F/src/flw-align-01.S/dut/DUT-spike.signature +signature-granularity=4 my.elf;

I wondered why the test is compiled with a machine architecture (-march=rv32i) that does not include floats. When I change this to "-march=rv32if" half of the error codes disappear, i.e. all "(...) Error: unrecognized opcode `flw (...)":

riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S: Assembler messages: riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:37: Error: unrecognized opcode fsreg f18,0(x15)' riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:41: Error: unrecognized opcodefsreg f28,8(x15)' (...) riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:129: Error: unrecognized opcode fsreg f19,64(x15)' riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:133: Error: unrecognized opcodefsreg f22,72(x15)' riscoftest/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S:137: Error: unrecognized opcode `fsreg f8,80(x15)'

I have also tried to run RISCOF version 1.22.1, but this instead had the issue of the two tests simulating infinitely - but they compile. The interactive debugger in Spike shows that the simulation is caught in an infinite loop after simulating the first floating point instruction contained in either of the tests:

(...) core 0: exception trap_instruction_access_fault, epc 0x00000000 core 0: tval 0x00000000 : core 0: exception trap_instruction_access_fault, epc 0x00000000 core 0: tval 0x00000000 : core 0: exception trap_instruction_access_fault, epc 0x00000000 core 0: tval 0x00000000 : core 0: exception trap_instruction_access_fault, epc 0x00000000 core 0: tval 0x00000000 : core 0: exception trap_instruction_access_fault, epc 0x00000000 core 0: tval 0x00000000 (...)

The make target used to run the particular tests does not inform Spike that the DUT supports float instructions. One of those targets is seen below:

.PHONY : TARGET27 TARGET27 : @cd (...)/riscoftest/riscof_work/rv32i_m/F/src/flw-align-01.S/dut; riscv32-unknown-elf-gcc -march=rv32if -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g -T (...)/spike/env/link.ld -I (...)/spike/env/ -I (...)/riscv-arch-test/riscv-test-suite/env (...)/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S -o my.elf -DTEST_CASE_1=True -DXLEN=32 -DFLEN=32 -mabi=ilp32 ; spike --isa=rv32imc +signature=(...)/riscof_work/rv32i_m/F/src/flw-align-01.S/dut/DUT-spike.signature +signature-granularity=4 my.elf;

Specifically, it is the option "spike --isa=rv32imc", which every test applies, that seems to cause the problem. If I run the target with a different ISA "--isa=rv32imdc" the test simulates correctly. Yet, reading the script used to generate the Makefile (spike/riscof_spike.py) shows that ISA support for float instructions never is considered for Spike's DUT.

I have also tried to run RISCOF version 1.21.0, but this also terminates with an error. The two tests causing me the issues was added to the riscv-arch-test repository at September 10.

Have you experienced any issues like this?

[pawks]

There is an error in the tests themselves. A fix will be released asap. Meanwhile you can test out riscof by providing each individual folders i.e rv32i_m/I, rv32i_m/M etc to run the rv32imc configuration. In case you want to try out the F tests, you should use the rv32imfc as the isa in the DUT ISA yaml. I have pushed in a fix for the second issue on this branch. Please use that branch to check.

[Don-Haugaard]

I can confirm that the fix on the branch seems to work as intended. After installing it with:

git clone -b improve-diff-reporting https://github.com/riscv-software-src/riscof.git
cd riscof
pip3 install --editable .

I get the following notifications when attempting to simulate the float tests:

   ERROR | Error in test: riscoftest2/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/flw-align-01.S
Test Selected without the relevant extensions being available on DUT.
   ERROR | Error in test: riscoftest2/riscv-arch-test/riscv-test-suite/rv32i_m/F/src/fsw-align-01.S
Test Selected without the relevant extensions being available on DUT.

All of the remaining tests are simulated correctly. Thank you!

Furthermore, though not sure this is the place to mention it, I noticed two other minor things:

1. The command mentioned in the quickstart guide for cloning the architectural tests is not working. The repository is called "arch-test", not "arch-tests", i.e. the correct command seem to be "riscof --verbose info arch-test --clone"
2. A minor spelling error is present when riscof opens the webbrowser, as the log writes "Openning test report in web-browser" instead of "Opening test report in web-browser" (This is a tiny thing - I am not trying to be picky!)

[neelgala]

@Don-Haugaard thanks for the feedback. the flw and fsw tests need a fix.. which I am working on (should be done soon). We are always happy to receive any help and feedback we can get. Let us know if you find any more issues - would like riscof to be as clean as possible before its official adoption.

@pawks can we update your branch with fixes for the issues mentioned above ?