riscv-software-src / riscv-ctg

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Cleanup for Floating point extensions. #34

Closed pawks closed 1 year ago

pawks commented 2 years ago
anuani24 commented 1 year ago

Hi,

Am started generating test case for RV32D in riscv_ctg 0.11.0 am getting error.Any ideas regarding this?

INFO | ** RISC-V Compliance Test Generator 0.11.0 **** INFO | Copyright (c) 2020, InCore Semiconductors Pvt. Ltd. INFO | All Rights Reserved. INFO | Copying env folder to Output directory. Traceback (most recent call last): File "/home/anusha/.local/bin/riscv_ctg", line 11, in load_entry_point('riscv-ctg', 'console_scripts', 'riscv_ctg')() File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1130, in call return self.main(args, kwargs) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1055, in main rv = self.invoke(ctx) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1404, in invoke return ctx.invoke(self.callback, *ctx.params) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 760, in invoke return __callback(args, **kwargs) File "/home/anusha/act/riscv-ctg/riscv_ctg/main.py", line 30, in cli ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst,z_inx) File "/home/anusha/act/riscv-ctg/riscv_ctg/ctg.py", line 128, in ctg op_template = utils.load_yamls(const.template_files) File "/home/anusha/act/riscv-ctg/riscv_ctg/utils.py", line 66, in load_yamls return dict(yaml.load(fp)) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/constructor.py", line 119, in get_single_data node = self.composer.get_single_node() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 76, in get_single_node document = self.compose_document() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 99, in compose_document node = self.compose_node(None, None) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 143, in compose_node node = self.compose_mapping_node(anchor) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 216, in compose_mapping_node while not self.parser.check_event(MappingEndEvent): File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 146, in check_event self.current_event = self.state() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 612, in parse_block_mapping_key raise ParserError( ruamel.yaml.parser.ParserError: while parsing a block mapping in "", line 2, column 1 expected , but found '' in "", line 12246, column 2

pawks commented 1 year ago

The error seems to be in the input cgf files. Which cgf file are you using?

anuani24 commented 1 year ago

riscv_ctg -v debug -d testd -cf sample_cgfs/dataset.cgf -cf sample_cgfs/sample_cgfs_fext/RV32D/fsgnj.d.cgf -bi rv32i -p 2 --flen 64 am running this command only

On Mon, Nov 21, 2022 at 11:43 AM S Pawan Kumar @.***> wrote:

The error seems to be in the input cgf files. Which cgf file are you using?

— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1321510208, or unsubscribe https://github.com/notifications/unsubscribe-auth/A37JVCO4JDWUBXWB5O2XYVDWJMHH3ANCNFSM5RZ4TRTQ . You are receiving this because you commented.Message ID: @.***>

anuani24 commented 1 year ago

Hi Sir,

Is there any idea to resolve the issue? pls share

On Mon, Nov 21, 2022 at 11:43 AM S Pawan Kumar @.***> wrote:

The error seems to be in the input cgf files. Which cgf file are you using?

— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1321510208, or unsubscribe https://github.com/notifications/unsubscribe-auth/A37JVCO4JDWUBXWB5O2XYVDWJMHH3ANCNFSM5RZ4TRTQ . You are receiving this because you commented.Message ID: @.***>

pawks commented 1 year ago

The canary values are wrongly defined in the current header file on main. Patched here.

anuani24 commented 1 year ago

Hi, Can you please share cgf file for RV32D extension?

anuani24 commented 1 year ago

Hi, Can you please share github link for riscv_ctg 0.11.0 version?

anuani24 commented 1 year ago

Hi, I have another doubt in riscv_ctg version 0.010.2, I am running RV32 F and RV32D test,am getting some error in RV32D test.here i have attached the log

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

On Tue, Nov 22, 2022 at 1:39 PM S Pawan Kumar @.***> wrote:

The canary values are wrongly defined in the current header file on main. Patched here https://github.com/riscv-non-isa/riscv-arch-test/pull/294.

— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1323267798, or unsubscribe https://github.com/notifications/unsubscribe-auth/A37JVCLE2S7BUXETNCNTQ6LWJR5U3ANCNFSM5RZ4TRTQ . You are receiving this because you commented.Message ID: @.***>

anuani24 commented 1 year ago

Hi sir,

Still am facing same issue.

riscv_ctg -v debug -d testd -cf sample_cgfs/dataset.cgf -cf sample_cgfs/sample_cgfs_fext/RV32D/fsgnj.d.cgf -bi rv32i -p 2 --flen=64 INFO | ** RISC-V Compliance Test Generator 0.11.0 **** INFO | Copyright (c) 2020, InCore Semiconductors Pvt. Ltd. INFO | All Rights Reserved. INFO | Copying env folder to Output directory. Traceback (most recent call last): File "/home/anusha/.local/bin/riscv_ctg", line 11, in load_entry_point('riscv-ctg', 'console_scripts', 'riscv_ctg')() File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1130, in call return self.main(args, kwargs) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1055, in main rv = self.invoke(ctx) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1404, in invoke return ctx.invoke(self.callback, *ctx.params) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 760, in invoke return __callback(args, **kwargs) File "/home/anusha/act/riscv-ctg/riscv_ctg/main.py", line 30, in cli ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst,z_inx) File "/home/anusha/act/riscv-ctg/riscv_ctg/ctg.py", line 137, in ctg op_template = utils.load_yamls(const.template_files) File "/home/anusha/act/riscv-ctg/riscv_ctg/utils.py", line 66, in load_yamls return dict(yaml.load(fp)) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/constructor.py", line 120, in get_single_data node = self.composer.get_single_node() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 76, in get_single_node document = self.compose_document() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 99, in compose_document node = self.compose_node(None, None) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 143, in compose_node node = self.compose_mapping_node(anchor) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 216, in compose_mapping_node while not self.parser.check_event(MappingEndEvent): File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 146, in check_event self.current_event = self.state() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 611, in parse_block_mapping_key raise ParserError( ruamel.yaml.parser.ParserError: while parsing a block mapping in "", line 2, column 1 expected , but found '' in "", line 12246, column 2

On Tue, Nov 22, 2022 at 1:39 PM S Pawan Kumar @.***> wrote:

The canary values are wrongly defined in the current header file on main. Patched here https://github.com/riscv-non-isa/riscv-arch-test/pull/294.

— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1323267798, or unsubscribe https://github.com/notifications/unsubscribe-auth/A37JVCLE2S7BUXETNCNTQ6LWJR5U3ANCNFSM5RZ4TRTQ . You are receiving this because you commented.Message ID: @.***>

anuani24 commented 1 year ago

Hi sir,

Pls give me any suggestions to resolve the above issues sir???

On Tue, 22 Nov, 2022, 2:40 pm Anusha R, @.***> wrote:

Hi sir,

Still am facing same issue.

riscv_ctg -v debug -d testd -cf sample_cgfs/dataset.cgf -cf sample_cgfs/sample_cgfs_fext/RV32D/fsgnj.d.cgf -bi rv32i -p 2 --flen=64 INFO | ** RISC-V Compliance Test Generator 0.11.0 **** INFO | Copyright (c) 2020, InCore Semiconductors Pvt. Ltd. INFO | All Rights Reserved. INFO | Copying env folder to Output directory. Traceback (most recent call last): File "/home/anusha/.local/bin/riscv_ctg", line 11, in load_entry_point('riscv-ctg', 'console_scripts', 'riscv_ctg')() File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1130, in call return self.main(args, kwargs) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1055, in main rv = self.invoke(ctx) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1404, in invoke return ctx.invoke(self.callback, *ctx.params) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 760, in invoke return __callback(args, **kwargs) File "/home/anusha/act/riscv-ctg/riscv_ctg/main.py", line 30, in cli ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst,z_inx) File "/home/anusha/act/riscv-ctg/riscv_ctg/ctg.py", line 137, in ctg op_template = utils.load_yamls(const.template_files) File "/home/anusha/act/riscv-ctg/riscv_ctg/utils.py", line 66, in load_yamls return dict(yaml.load(fp)) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/constructor.py", line 120, in get_single_data node = self.composer.get_single_node() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 76, in get_single_node document = self.compose_document() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 99, in compose_document node = self.compose_node(None, None) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 143, in compose_node node = self.compose_mapping_node(anchor) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 216, in compose_mapping_node while not self.parser.check_event(MappingEndEvent): File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 146, in check_event self.current_event = self.state() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 611, in parse_block_mapping_key raise ParserError( ruamel.yaml.parser.ParserError: while parsing a block mapping in "", line 2, column 1 expected , but found '' in "", line 12246, column 2

On Tue, Nov 22, 2022 at 1:39 PM S Pawan Kumar @.***> wrote:

The canary values are wrongly defined in the current header file on main. Patched here https://github.com/riscv-non-isa/riscv-arch-test/pull/294.

— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1323267798, or unsubscribe https://github.com/notifications/unsubscribe-auth/A37JVCLE2S7BUXETNCNTQ6LWJR5U3ANCNFSM5RZ4TRTQ . You are receiving this because you commented.Message ID: @.***>

pawks commented 1 year ago

This error is fixed on #53

anuani24 commented 1 year ago

Hi, I have one doubt in riscv_ctg version 0.010.2, I am running RV32 F and RV32D test, am getting some error in riscof RV32D test.here i have attached the log

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

On Wed, Nov 23, 2022 at 11:05 AM S Pawan Kumar @.***> wrote:

This error is fixed on #53 https://github.com/riscv-software-src/riscv-ctg/pull/53

— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1324574365, or unsubscribe https://github.com/notifications/unsubscribe-auth/A37JVCJ3TVFRIM23LCLEVGDWJWULZANCNFSM5RZ4TRTQ . You are receiving this because you commented.Message ID: @.***>

anuani24 commented 1 year ago

Hi sir,

Am running RV32D test in riscv_ctg version 0.10.2 and generated all test cases.When i am running RV32D test in riscof version 1.25.2,am getting the error message in log,

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

Pls give me suggestions to resolve this issue.

On Wed, Nov 23, 2022 at 11:05 AM S Pawan Kumar @.***> wrote:

This error is fixed on #53 https://github.com/riscv-software-src/riscv-ctg/pull/53

— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1324574365, or unsubscribe https://github.com/notifications/unsubscribe-auth/A37JVCJ3TVFRIM23LCLEVGDWJWULZANCNFSM5RZ4TRTQ . You are receiving this because you commented.Message ID: @.***>

anuani24 commented 1 year ago

Hi sir,

Please send me any suggestion to resolve the above issue.

On Wed, 23 Nov, 2022, 11:18 am Anusha R, @.***> wrote:

Hi sir,

Am running RV32D test in riscv_ctg version 0.10.2 and generated all test cases.When i am running RV32D test in riscof version 1.25.2,am getting the error message in log,

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

Pls give me suggestions to resolve this issue.

On Wed, Nov 23, 2022 at 11:05 AM S Pawan Kumar @.***> wrote:

This error is fixed on #53 https://github.com/riscv-software-src/riscv-ctg/pull/53

— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1324574365, or unsubscribe https://github.com/notifications/unsubscribe-auth/A37JVCJ3TVFRIM23LCLEVGDWJWULZANCNFSM5RZ4TRTQ . You are receiving this because you commented.Message ID: @.***>

anuani24 commented 1 year ago

Hi sir,

Please send me any suggestion to resolve the above issue.

On Thu, Nov 24, 2022 at 6:12 AM Anusha R @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Wed, 23 Nov, 2022, 11:18 am Anusha R, @.***> wrote:

Hi sir,

Am running RV32D test in riscv_ctg version 0.10.2 and generated all test cases.When i am running RV32D test in riscof version 1.25.2,am getting the error message in log,

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

Pls give me suggestions to resolve this issue.

On Wed, Nov 23, 2022 at 11:05 AM S Pawan Kumar @.***> wrote:

This error is fixed on #53 https://github.com/riscv-software-src/riscv-ctg/pull/53

— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1324574365, or unsubscribe https://github.com/notifications/unsubscribe-auth/A37JVCJ3TVFRIM23LCLEVGDWJWULZANCNFSM5RZ4TRTQ . You are receiving this because you commented.Message ID: @.***>

allenjbaum commented 1 year ago

Try pulling from the latest riscv_ctg; the version number was not updated (this is being fixed) but the problem you are seeing should be fixed.

On Wed, Nov 23, 2022 at 11:11 PM anuani24 @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Thu, Nov 24, 2022 at 6:12 AM Anusha R @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Wed, 23 Nov, 2022, 11:18 am Anusha R, @.***> wrote:

Hi sir,

Am running RV32D test in riscv_ctg version 0.10.2 and generated all test cases.When i am running RV32D test in riscof version 1.25.2,am getting the error message in log,

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

Pls give me suggestions to resolve this issue.

On Wed, Nov 23, 2022 at 11:05 AM S Pawan Kumar @.***> wrote:

This error is fixed on #53 https://github.com/riscv-software-src/riscv-ctg/pull/53

— Reply to this email directly, view it on GitHub < https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1324574365 , or unsubscribe < https://github.com/notifications/unsubscribe-auth/A37JVCJ3TVFRIM23LCLEVGDWJWULZANCNFSM5RZ4TRTQ

. You are receiving this because you commented.Message ID: @.***>

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anuani24 commented 1 year ago

Hi sir, Actually I have tried latest version 0.11.0,in that i can't able to generate test i n riscv- ctg it will throwing parse error

On Fri, 25 Nov, 2022, 1:21 am Allen Baum, @.***> wrote:

Try pulling from the latest riscv_ctg; the version number was not updated (this is being fixed) but the problem you are seeing should be fixed.

On Wed, Nov 23, 2022 at 11:11 PM anuani24 @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Thu, Nov 24, 2022 at 6:12 AM Anusha R @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Wed, 23 Nov, 2022, 11:18 am Anusha R, @.***> wrote:

Hi sir,

Am running RV32D test in riscv_ctg version 0.10.2 and generated all test cases.When i am running RV32D test in riscof version 1.25.2,am getting the error message in log,

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

Pls give me suggestions to resolve this issue.

On Wed, Nov 23, 2022 at 11:05 AM S Pawan Kumar @.***> wrote:

This error is fixed on #53 https://github.com/riscv-software-src/riscv-ctg/pull/53

— Reply to this email directly, view it on GitHub <

https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1324574365

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anuani24 commented 1 year ago

Hi, In latest version of riscv-ctg ,am getting this issue, INFO | ** RISC-V Compliance Test Generator 0.11.0 **** INFO | Copyright (c) 2020, InCore Semiconductors Pvt. Ltd. INFO | All Rights Reserved. INFO | Copying env folder to Output directory. Traceback (most recent call last): File "/home/anusha/.local/bin/riscv_ctg", line 11, in load_entry_point('riscv-ctg', 'console_scripts', 'riscv_ctg')() File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1130, in call return self.main(args, kwargs) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1055, in main rv = self.invoke(ctx) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1404, in invoke return ctx.invoke(self.callback, *ctx.params) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 760, in invoke return __callback(args, **kwargs) File "/home/anusha/act/riscv-ctg/riscv_ctg/main.py", line 30, in cli ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst,z_inx) File "/home/anusha/act/riscv-ctg/riscv_ctg/ctg.py", line 137, in ctg op_template = utils.load_yamls(const.template_files) File "/home/anusha/act/riscv-ctg/riscv_ctg/utils.py", line 66, in load_yamls return dict(yaml.load(fp)) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/constructor.py", line 120, in get_single_data node = self.composer.get_single_node() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 76, in get_single_node document = self.compose_document() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 99, in compose_document node = self.compose_node(None, None) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 143, in compose_node node = self.compose_mapping_node(anchor) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 216, in compose_mapping_node while not self.parser.check_event(MappingEndEvent): File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 146, in check_event self.current_event = self.state() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 611, in parse_block_mapping_key raise ParserError( ruamel.yaml.parser.ParserError: while parsing a block mapping in "", line 2, column 1 expected , but found '' in "", line 12246, column 2

On Fri, Nov 25, 2022 at 9:17 AM Anusha R @.***> wrote:

Hi sir, Actually I have tried latest version 0.11.0,in that i can't able to generate test i n riscv- ctg it will throwing parse error

On Fri, 25 Nov, 2022, 1:21 am Allen Baum, @.***> wrote:

Try pulling from the latest riscv_ctg; the version number was not updated (this is being fixed) but the problem you are seeing should be fixed.

On Wed, Nov 23, 2022 at 11:11 PM anuani24 @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Thu, Nov 24, 2022 at 6:12 AM Anusha R @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Wed, 23 Nov, 2022, 11:18 am Anusha R, @.***> wrote:

Hi sir,

Am running RV32D test in riscv_ctg version 0.10.2 and generated all test cases.When i am running RV32D test in riscof version 1.25.2,am getting the error message in log,

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

Pls give me suggestions to resolve this issue.

On Wed, Nov 23, 2022 at 11:05 AM S Pawan Kumar @.***> wrote:

This error is fixed on #53 https://github.com/riscv-software-src/riscv-ctg/pull/53

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https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1324574365

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anuani24 commented 1 year ago

Can you please any suggestion to resolve the issue?

On Fri, Nov 25, 2022 at 11:08 AM Anusha R @.***> wrote:

Hi, In latest version of riscv-ctg ,am getting this issue, INFO | ** RISC-V Compliance Test Generator 0.11.0 **** INFO | Copyright (c) 2020, InCore Semiconductors Pvt. Ltd. INFO | All Rights Reserved. INFO | Copying env folder to Output directory. Traceback (most recent call last): File "/home/anusha/.local/bin/riscv_ctg", line 11, in load_entry_point('riscv-ctg', 'console_scripts', 'riscv_ctg')() File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1130, in call return self.main(args, kwargs) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1055, in main rv = self.invoke(ctx) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1404, in invoke return ctx.invoke(self.callback, *ctx.params) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 760, in invoke return __callback(args, **kwargs) File "/home/anusha/act/riscv-ctg/riscv_ctg/main.py", line 30, in cli ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst,z_inx) File "/home/anusha/act/riscv-ctg/riscv_ctg/ctg.py", line 137, in ctg op_template = utils.load_yamls(const.template_files) File "/home/anusha/act/riscv-ctg/riscv_ctg/utils.py", line 66, in load_yamls return dict(yaml.load(fp)) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/constructor.py", line 120, in get_single_data node = self.composer.get_single_node() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 76, in get_single_node document = self.compose_document() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 99, in compose_document node = self.compose_node(None, None) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 143, in compose_node node = self.compose_mapping_node(anchor) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 216, in compose_mapping_node while not self.parser.check_event(MappingEndEvent): File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 146, in check_event self.current_event = self.state() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 611, in parse_block_mapping_key raise ParserError( ruamel.yaml.parser.ParserError: while parsing a block mapping in "", line 2, column 1 expected , but found '' in "", line 12246, column 2

On Fri, Nov 25, 2022 at 9:17 AM Anusha R @.***> wrote:

Hi sir, Actually I have tried latest version 0.11.0,in that i can't able to generate test i n riscv- ctg it will throwing parse error

On Fri, 25 Nov, 2022, 1:21 am Allen Baum, @.***> wrote:

Try pulling from the latest riscv_ctg; the version number was not updated (this is being fixed) but the problem you are seeing should be fixed.

On Wed, Nov 23, 2022 at 11:11 PM anuani24 @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Thu, Nov 24, 2022 at 6:12 AM Anusha R @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Wed, 23 Nov, 2022, 11:18 am Anusha R, @.***> wrote:

Hi sir,

Am running RV32D test in riscv_ctg version 0.10.2 and generated all test cases.When i am running RV32D test in riscof version 1.25.2,am getting the error message in log,

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

Pls give me suggestions to resolve this issue.

On Wed, Nov 23, 2022 at 11:05 AM S Pawan Kumar @.***> wrote:

This error is fixed on #53 https://github.com/riscv-software-src/riscv-ctg/pull/53

— Reply to this email directly, view it on GitHub <

https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1324574365

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anuani24 commented 1 year ago

Can you please give any suggestion to resolve the issue?

On Fri, Nov 25, 2022 at 11:40 AM Anusha R @.***> wrote:

Can you please any suggestion to resolve the issue?

On Fri, Nov 25, 2022 at 11:08 AM Anusha R @.***> wrote:

Hi, In latest version of riscv-ctg ,am getting this issue, INFO | ** RISC-V Compliance Test Generator 0.11.0 **** INFO | Copyright (c) 2020, InCore Semiconductors Pvt. Ltd. INFO | All Rights Reserved. INFO | Copying env folder to Output directory. Traceback (most recent call last): File "/home/anusha/.local/bin/riscv_ctg", line 11, in load_entry_point('riscv-ctg', 'console_scripts', 'riscv_ctg')() File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1130, in call return self.main(args, kwargs) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1055, in main rv = self.invoke(ctx) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 1404, in invoke return ctx.invoke(self.callback, *ctx.params) File "/home/anusha/.local/lib/python3.8/site-packages/click/core.py", line 760, in invoke return __callback(args, **kwargs) File "/home/anusha/act/riscv-ctg/riscv_ctg/main.py", line 30, in cli ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst,z_inx) File "/home/anusha/act/riscv-ctg/riscv_ctg/ctg.py", line 137, in ctg op_template = utils.load_yamls(const.template_files) File "/home/anusha/act/riscv-ctg/riscv_ctg/utils.py", line 66, in load_yamls return dict(yaml.load(fp)) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/constructor.py", line 120, in get_single_data node = self.composer.get_single_node() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 76, in get_single_node document = self.compose_document() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 99, in compose_document node = self.compose_node(None, None) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 143, in compose_node node = self.compose_mapping_node(anchor) File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/composer.py", line 216, in compose_mapping_node while not self.parser.check_event(MappingEndEvent): File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 146, in check_event self.current_event = self.state() File "/home/anusha/.local/lib/python3.8/site-packages/ruamel/yaml/parser.py", line 611, in parse_block_mapping_key raise ParserError( ruamel.yaml.parser.ParserError: while parsing a block mapping in "", line 2, column 1 expected , but found '' in "", line 12246, column 2

On Fri, Nov 25, 2022 at 9:17 AM Anusha R @.***> wrote:

Hi sir, Actually I have tried latest version 0.11.0,in that i can't able to generate test i n riscv- ctg it will throwing parse error

On Fri, 25 Nov, 2022, 1:21 am Allen Baum, @.***> wrote:

Try pulling from the latest riscv_ctg; the version number was not updated (this is being fixed) but the problem you are seeing should be fixed.

On Wed, Nov 23, 2022 at 11:11 PM anuani24 @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Thu, Nov 24, 2022 at 6:12 AM Anusha R @.***> wrote:

Hi sir,

Please send me any suggestion to resolve the above issue.

On Wed, 23 Nov, 2022, 11:18 am Anusha R, @.***> wrote:

Hi sir,

Am running RV32D test in riscv_ctg version 0.10.2 and generated all test cases.When i am running RV32D test in riscof version 1.25.2,am getting the error message in log,

mem[X,0x80000124] -> 0x7FD3 mem[X,0x80000126] -> 0x03EF [78] [M]: 0x80000124 (0x03EF7FD3) fadd.d ft11, ft10, ft10, dyn f31 <- 0x0000000000000000

mem[X,0x80000128] -> 0x2273 mem[X,0x8000012A] -> 0x0030 [79] [M]: 0x80000128 (0x00302273) csrrs tp, fcsr, zero CSR fcsr -> 0x00000000 x4 <- 0x00000000

mem[X,0x8000012C] -> 0xB027 mem[X,0x8000012E] -> 0x01F0

trapping from M to M to handle misaliged-store/amo handling exc#0x06 at priv M with tval 0x8000A614 CSR mstatus <- 0x80007800

Pls give me suggestions to resolve this issue.

On Wed, Nov 23, 2022 at 11:05 AM S Pawan Kumar @.***> wrote:

This error is fixed on #53 https://github.com/riscv-software-src/riscv-ctg/pull/53

— Reply to this email directly, view it on GitHub <

https://github.com/riscv-software-src/riscv-ctg/issues/34#issuecomment-1324574365

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